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SNJ54AS885JT

Part # SNJ54AS885JT
Description Magnitude Comparator 8-Bit 24-Pin CDIP Tube - RAL
Category IC
Availability In Stock
Qty 39
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33 + $17.82097
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
H or L
Latch
Enable
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
13
14
P > QOUT
P < QOUT
AS885
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LSP MSP
MSB
LSB
MSB
24 Bit
24.4 ns
Typical
16 Bit
19 ns
Typical
Figure 2. Fastest Cascading Arrangement for Comparing 16-Bit or 24-Bit Words
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
V
OH
V
OL
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
R
L
= R1 = R2
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR 1 MHz, t
r
= t
f
= 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
5962-89757013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8975701KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8975701LA ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type
SN54AS885JT ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type
SN74AS885DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885DWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885DWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885DWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AS885NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS885NT3 OBSOLETE PDIP NT 24 TBD Call TI Call TI
SN74AS885NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SNJ54AS885FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AS885JT ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type
SNJ54AS885W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2007
Addendum-Page 1
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