Name: SNJ54AC374W
SKU: SNJ54AC374W
Price: 18.38349 USD
Availability: InStock

 

   

  

SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 9.5 ns at 5 V

D 3-State Noninverting Outputs Drive Bus

Lines Directly

D Full Parallel Access for Loading

description/ordering information

These 8-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight flip-flops of the ’AC374 devices are

D-type edge-triggered flip-flops. On the positive

transition of the clock (CLK) input, the Q outputs

are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE

) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

the increased drive provide the capability to drive

bus lines in bus-organized systems without need

for interface or pullup components.

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC374N SN74AC374N

SOIC − DW

Tube SN74AC374DW

AC374

SOIC − DW

Tape and reel SN74AC374DWR

AC374

−40°C to 85°C

SOP − NS Tape and reel SN74AC374NSR AC374

−40 C to 85 C

SSOP − DB Tape and reel SN74AC374DBR AC374

TSSOP − PW

Tube SN74AC374PW

AC374

TSSOP − PW

Tape and reel SN74AC374PWR

AC374

CDIP − J Tube SNJ54AC374J SNJ54AC374J

−55°C to 125°C

CFP − W Tube SNJ54AC374W SNJ54AC374W

−55 C to 125 C

LCCC − FK Tube SNJ54AC374FK SNJ54AC374FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

  ! " #$%! "  &$'(#! )!%*

)$#!" # ! "&%##!" &% !+% !%"  %," "!$%!"

"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%

!%"!/  (( &%!%"*

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

CLK

SN54AC374 ...J OR W PACKAGE

SN74AC374 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

SN54AC374...FK PACKAGE

(TOP VIEW)

CLK

 &)$#!" #&(! ! 01 (( &%!%" % !%"!%)

$(%"" !+%-"% !%)*  (( !+% &)$#!" &)$#!

&#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"*

 

   

  

SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE CLK D

OUTPUT

L ↑ H H

L ↑ LL

L H or L X Q

H X X Z

logic diagram (positive logic)

CLK

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) −0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Note 1) −0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0 or V

> V

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0 or V

> V

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

= 0 to V

) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

 

   

  

SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54AC374 SN74AC374

UNIT

MIN MAX MIN MAX

UNIT

Supply voltage 2 6 2 6 V

= 3 V 2.1 2.1

High-level input voltage

= 4.5 V

3.15 3.15

High-level input voltage

= 5.5 V 3.85 3.85

= 3 V 0.9 0.9

Low-level input voltage

= 4.5V

1.35 1.35

Low-level input voltage

= 5.5 V 1.65 1.65

Input voltage 0 V

0 V

Output voltage 0 V

0 V

= 3 V −12 −12

High-level output current

= 4.5 V

−24 −24

High-level output current

= 5.5 V −24 −24

= 3 V 12 12

Low-level output current

= 4.5 V

24 24

Low-level output current

= 5.5 V 24 24

∆t/∆v Input transition rise or fall rate 8 8 ns/V

Operating free-air temperature −55 125 −40 85 °C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

= 25°C SN54AC374 SN74AC374

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN MAX MIN MAX

UNIT

3 V 2.9 2.9 2.9

= −50 µA

4.5 V 4.4 4.4 4.4

= −50 µA

5.5 V 5.4 5.4 5.4

= −12 mA 3 V 2.56 2.4 2.46

= −24 mA

4.5 V 3.86 3.7 3.76

= −24 mA

5.5 V 4.86 4.7 4.76

3 V 0.1 0.1 0.1

= 50 µA

4.5 V 0.1 0.1 0.1

= 50 µA

5.5 V 0.1 0.1 0.1

= 12 mA 3 V 0.36 0.5 0.44

= 24 mA

4.5 V 0.36 0.5 0.44

= 24 mA

5.5 V 0.36 0.5 0.44

= V

or GND 5.5 V ±0.1 ±1 ±1 µA

= V

or GND 5.5 V ±0.25 ±5 ±2.5 µA

= V

or GND, I

= 0 5.5 V 4 80 40 µA

= V

or GND 5 V 4.5 pF

Part #	SNJ54AC374W
Description	Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-
Category	IC
Availability	In Stock
Qty	7

Qty	Price
1 - 1	$18.38349
2 - 2	$14.62323
3 - 4	$13.78762
5 - 5	$12.81274
6 +	$11.42005

SNJ54AC374W

Related Items

Technical Document