Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

SNJ54ABTH18502AHV

Part # SNJ54ABTH18502AHV
Description Bus XCVR Dual 18-CH 3-ST 68-Pin CFPAK Tube - Rail/Tube
Category IC
Availability In Stock
Qty 18
Qty Price
1 - 1 $146.68567
2 - 2 $116.68179
3 - 4 $110.01425
5 - 7 $102.23547
8 + $91.12292
Manufacturer Available Qty
Texas Instruments
Date Code: 9643
  • Shipping Freelance Stock: 1
    Ships Immediately
Texas Instruments
Date Code: 9600
  • Shipping Freelance Stock: 17
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Members of the Texas Instruments
SCOPE
Family of Testability Products
Members of the Texas Instruments
Widebus
Family
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port
and Boundary-Scan Architecture
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
B-Port Outputs of ’ABTH182502A Devices
Have Equivalent 25- Series Resistors, So
No External Resistors Are Required
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
One Boundary-Scan Cell Per I/O
Architecture Improves Scan Efficiency
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
V
NC
TMS
1CLKBA
1A2
1A1
1OEAB
GND
1LEAB
1CLKAB
TDO
1LEBA
1OEBA
GND
1B1
1B2
1B3
CC
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
NC
TCK
2CLKBA
2LEBA
2A9
GND
2OEAB
2LEAB
2CLKAB
TDI
2A7
2A8
GND
2OEBA
2B9
2B8
SN54ABTH18502A, SN54ABTH182502A . . . HV PACKAGE
(TOP VIEW)
CC
V
NC – No internal connection
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29 30 31 32 33 34
87 65493168672
35 36 37 38 39
66 65
27
64 63 62 61
40 41 42 43
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
18 19
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21 22 23 24
63 62 61 60 5964 58 56 55 5457
25 26 27 28 29
53 52
17
51 50 49
30 31 32
1OEAB
GND
1CLKAB
TDO
1A2
1A1
1LEAB
V
1LEBA
1OEBA
1B1
1B2
TMS
1CLKBA
GND
1B3
2A9
GND
2LEAB
2CLKAB
2A7
2A8
2OEAB
TDI
2CLKBA
2LEBA
2OEBA
2B9
V
TCK
GND
2B8
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B4
1B5
1B6
GND
1B7
1B8
1B9
V
CC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
CC
CC
SN74ABTH18502A, SN74ABTH182502A . . . PM PACKAGE
(TOP VIEW)
description
The ’ABTH18502A and ’ABTH182502A scan test devices with 18-bit universal bus transceivers are members
of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB
and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the
B outputs are active. When OEAB
is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited and the test circuitry
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs
boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin
architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A
PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count
addressing scheme is useful.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The B-port outputs of ’ABTH182502A, which are designed to source or sink up to 12 mA, include 25- series
resistors to reduce overshoot and undershoot.
The SN54ABTH18502A and SN54ABTH182502A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74ABTH18502A and SN74ABTH182502A are characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(normal mode, each register)
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L L L X B
0
L L LL
L L HH
L HXLL
L HXHH
H X X X Z
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA
, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
1234567NEXT