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DP83847ALQA56A

Part # DP83847ALQA56A
Description IC ETHERNET TRANSCEIVER 56WQFN
Category IC
Availability In Stock
Qty 4
Qty Price
1 + $3.29619
Manufacturer Available Qty
National Semiconductor Corp
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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DP83847
5.0 Register Block
Table 6. Register Map
Offset
Access Tag Description
Hex Decimal
00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX
08h-Fh 8-15 RESERVED RESERVED
Extended Registers
10h 16 RO PHYSTS PHY Status Register
11h-13h 17-19 RESERVED RESERVED
14h 20 RW FCSCR False Carrier Sense Counter Register
15h 21 RW RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RESERVED RESERVED
18h 24 RW RESERVED RESERVED
19h 25 RW PHYCTRL PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL CD Test Control Register
1Ch-1Fh 28 RW RESERVED RESERVED
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DP83847
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Basic Mode Control Register
00h BMCR Reset Loopback Speed Se-
lect
Auto-Neg
Enable
Power
down
Isolate Restart
Auto-Neg
Duplex Collision
Test
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Basic Mode Status Register
01h BMSR 100Base-
T4
100Base-
TX FDX
100Base-
TX HDX
10Base-
T
FDX
10Base-
T
HDX
Reserved Reserved Reserved Reserved MF Pre-
amble
Suppress
Auto-Neg
Complete
Remote
Fault
Auto-Neg
Ability
Link
Status
Jabber
Detect
Extended
Capability
PHY Identifier Register 1
02h PHYIDR1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB
PHY Identifier Register 2
03h PHYIDR2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
MDL_
REV
MDL_
REV
MDL_
REV
MDL_
REV
Auto-Negotiation Advertisement Register
04h ANAR Next Page
Ind
Reserved Remote
Fault
Reserved Reserved PAUSE T4 TX_FD TX 10_FD 10 Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Auto-Negotiation Link Partner Ability Regis-
ter (Base Page)
05h ANLPAR Next Page
Ind
ACK Remote
Fault
Reserved Reserved Reserved T4 TX_FD TX 10_FD 10 Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Auto-Negotiation Link Partner Ability Regis-
ter Next Page
05h ANLPARNP Next Page
Ind
ACK Message
Page
ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code
Auto-Negotiation Expansion Register
06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_
ABLE
NP_
ABLE
PAGE_
RX
LP_AN_
ABLE
Auto-Negotiation Next Page TX Register
07h ANNPTR Next Page
Ind
Reserved Message
Page
ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
RESERVED
08-0fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXTENDED REGISTERS
PHY Status Register
10h PHYSTS Reserved Reserved Rx Err
Latch
Polarity
Status
False Car-
rier Sense
Signal De-
tect
Descram
Lock
Page
Receive
Reserved Remote
Fault
Jabber
Detect
Auto-Neg
Complete
Loopback
Status
Duplex
Status
Speed
Status
Link
Status
RESERVED
11-13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
False Carrier Sense Counter Register
14h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT
Receive Error Counter Register
15h RECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RXER-
CNT
RXER-
CNT
RXER-
CNT
RXER-
CNT
RXER-
CNT
RXER-
CNT
RXER-
CNT
RXER-
CNT
PCS Sub-Layer Configuration and Status
Register
16h PCSR Reserved Reserved Reserved BYP_
4B5B
FREE_
CLK
TQ_EN SD_FOR
CE_PMA
SD_
OPTION
Unused Reserved FORCE_
100_OK
Reserved Reserved NRZI_
BYPASS
SCRAM_
BYPASS
DE
SCRAM_
BYPASS
RESERVED
17-18h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PHY Control Register
19h PHYCTRL Unused Unused Unused Unused PSR_15 BIST_
STATUS
BIST_
START
BP_
STRETC
H
PAUSE_
STS
LED_
CNFG
LED_
CNFG
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
10Base-T Status/Control Register
1Ah 10BTSCR Unused Unused Unused Unused Unused Unused Unused Loopback
_10_dis
LP_DIS Force_
Link_10
Reserved Polarity Reserved Reserved Hrtbeat
_Dis
Jabber
_Dis
CD Test Control Register
1Bh CDCTRL CD_Enabl
e
DCD_
Comp
FIL_TTL rise-
Time[1]
rise-
Time[0]
fallTime[1] fallTime[0] cdTestEn Reserved Reserved Reserved cdPattEn_
10
cdPatEn_
100
10meg_
patt_gap
cdPatt-
Sel[1]
cdPatt-
Sel[0]
RESERVED
1C-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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DP83847
5.1 Register Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
RW=Read Write access
SC=Register sets on event occurrence and Self-Clears when event ends
RW/SC =Read Write access/Self Clearing bit
RO=Read Only access
COR = Clear on Read
RO/COR=Read Only, Clear on Read
RO/P=Read Only, Permanently set to a default value
LL=Latched Low and held until read, based upon the occurrence of the corresponding event
LH=Latched High and held until read, based upon the occurrence of the corresponding event
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