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DP83840AVCE

Part # DP83840AVCE
Description IC ETHERNET PHYS LAYER 100QFP
Category IC
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Technical Document


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DP83840A
DP83840A 10/100 Mb/s Ethernet Physical Layer
Literature Number: SNLS006A
1
National SemiconductorVersion A
March 1997
DP83840A 10/100 Mb/s Ethernet Physical Layer
General Description
The DP83840A is a Physical Layer device for Ethernet
10BASE-T and 100BASE-X using category 5 Unshielded,
Type 1 Shielded and Fiber Optic cables.
This VLSI device is designed for easy implementation of
10/100 Mb/s Ethernet LANs. It interfaces to the PMD sub-
layer through National Semiconductor's DP83223 Twisted
Pair Transceiver, and to the MAC layer through a Media
Independent Interface (MII), ensuring interoperability
between products from different vendors.
The DP83840A is designed with National Semiconductor's
BiCMOS process. Its system architecture is based on the
integration of several of National Semiconductor's industry
proven core technologies:
10BASE-T ENDEC/Transceiver module to provide the 10
Mb/s IEEE 802.3 functions
Clock Recovery/Generator Modules from National
Semiconductor's leading FDDI product
FDDI Stream Cipher (Cyclone)
100BASE-X physical coding sub-layer (PCS) and control
logic that integrate the core modules into a dual speed
Ethernet physical layer controller
System Diagram
Features
IEEE 802.3 10BASE-T compatible--ENDEC and UTP/
STP transceivers and filters built-in
IEEE 802.3u 100BASE-X compatible--support for 2 pair
Category 5 UTP (100m), Type 1 STP and Fiber Optic
Transceivers--Connects directly to the DP83223 Twisted
Pair Transceiver
ANSI X3T12 TP-PMD compatible
IEEE 802.3u Auto-Negotiation for automatic speed
selection
IEEE 802.3u compatible Media Independent Interface
(MII) with Serial Management Interface
Integrated high performance 100 Mb/s clock recovery
circuitry requiring no external filters
Full Duplex support for 10 and 100 Mb/s
MII Serial 10 Mb/s output mode
Fully configurable node and repeater modes--allows
operation in either application
Programmable loopback modes for easy system
diagnostics
Flexible LED support
IEEE 1149.1 Standard Test Access Port and Boundary-
Scan compatible
Small footprint 100-pin PQFP package
Individualized scrambler seed for multi-PHY applications
DP83840A
10/100 Mb/s Ethernet Physical Layer
10 AND/OR 100 Mb/s
ETHERNET MAC OR
REPEATER/SWITCH
PORT
DP83840A
10/100 Mb/s
ETHERNET PHYSICAL LAYER
CLOCKS
STATUS
LEDS
DP83223
100BASE-TX
TRANSCEIVER
MAGNETICS
RJ-45
10BASE-T
OR
100BASE-TX
MII
10BASE-T
100BASE-FX
TRANSCEIVER
Obsolete
2
National SemiconductorVersion A
DP83840A 10/100 Mb/s Ethernet Physical Layer
Block Diagram
SERIAL
MANAGEMENT
MII
IEEE
1149.1
(JTAG)
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDIO
MDC
COL
CRS
RX_ER
RX_DV
RXD[3:0]
RX_CLK
MII INTERFACE/CONTROL
TEST
ACCESS
PORT
LED
DRIVERS
LED 1-5
100 Mb/s
RECEIVE
CLOCK
DATA
REGISTERS
AUTO
NEGOTIATION
RX STATE
MACHINE
PCS
SSD
DETECT
CARRIER
SENSE
COLLISION
DETECTION
CODE-GROUP
DECODER
CODE-GROUP
ALIGNMENT
DESCRAMBLER
RD +/-
SD +/-
SERIAL TO
PARALLEL
CRM
NRZI TO NRZ
100BASE-X
10BASE-T
MII
NODE/
REPEATER
PCS
CONTROL
10BASE-T
TX
UTP/STP
RX
AUTO
NEGOTIATION
100 Mb/s
RECEIVE
CLOCK
DATA
PCS
CODE-GROUP
ENCODER AND
INJECTION
SCRAMBLER
CLOCK(S)
PARALLEL TO
SERIAL
100BASE-X
RECEIVE INTERFACE
RXI +/-
TXS+/-
TXU+/-
TD +/-
100BASE-X
TRANSMIT INTERFACE
10 BASE-T
INTERFACE
CGM
NRZ / NRZI
TX STATE
MACHINE
RX_EN
Obsolete
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