12 www.national.com

DP83847

The BMSR also provides status on:

— Whether Auto-Negotiation is complete

— Whether the Link Partner is advertising that a remote

fault has occurred

— Whether valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the

DP83847. All available abilities are transmitted by default,

but any ability can be suppressed by writing to the ANAR.

Updating the ANAR to suppress an ability is one way for a

management agent to change (force) the technology that is

used.

The Auto-Negotiation Link Partner Ability Register

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

— Whether a Parallel Detect Fault has occurred

— Whether the Link Partner supports the Next Page func-

tion

— Whether the DP83847 supports the Next Page function

— Whether the current page being exchanged by Auto-Ne-

gotiation has been received

— Whether the Link Partner supports Auto-Negotiation

2.1.3 Auto-Negotiation Parallel Detection

The DP83847 supports the Parallel Detection function as

defined in the IEEE 802.3u specification. Parallel Detection

requires both the 10 Mb/s and 100 Mb/s receivers to moni-

tor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this informa-

tion to configure the correct technology in the event that the

Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

If the DP83847 completes Auto-Negotiation as a result of

Parallel Detection, bits 5 and 7 within the ANLPAR register

will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter-

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able

bit, once the Auto-Negotiation Complete bit is set. If config-

ured for parallel detect mode and any condition other than

a single good link occurs then the parallel detect fault bit

will set.

2.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu-

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83847 to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83847 will resume Auto-Negotiation after the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83847 has been initial-

ized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit 12 (Auto-Negotiation Enable) of the Basic Mode Control

Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com-

plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

2.2 PHY Address and LEDs

The 5 PHY address inputs pins are shared with the LED

pins as shown below.

The DP83847 can be set to respond to any of 32 possible

PHY addresses. Each DP83847 or port sharing an MDIO

bus in a system must have a unique physical address.

Refer to Section 3.1.4, PHY Address Sensing section for

more details.

The state of each of the PHYAD inputs latched into the

PHYCTRL register bits [4:0]at system power-up/reset

depends on whether a pull-up or pull-down resistor has

been installed for each pin. For further detail relating to the

latch-in timing requirements of the PHY Address pins, as

well as the other hardware configuration pins, refer to the

Reset summary in Section 4.0.

Since the PHYAD strap options share the LED output pins,

the external components required for strapping and LED

usage must be considered in order to avoid contention.

Specifically, when the LED outputs are used to drive LEDs

directly, the active state of each output driver is dependent

on the logic level sampled by the corresponding PHYAD

input upon power-up/reset. For example, if a given PHYAD

input is resistively pulled low then the corresponding output

will be configured as an active high driver. Conversely, if a

Table 2. PHY Address Mapping

Pin # PHYAD Function LED Function

23 PHYAD0 Duplex

22 PHYAD1 COL

21 PHYAD2 Good Link

20 PHYAD3 TX Activity

19 PHYAD4 RX Activity

18 n/a Speed

13 www.national.com

DP83847

given PHYAD input is resistively pulled high, then the cor-

responding output will be configured as an active low

driver. Refer to Figure 1 for an example of a PHYAD con-

nection to external components. In this example, the

PHYAD strapping results in address 00011 (03h).

The adaptive nature of the LED outputs helps to simplify

potential implementation issues of these dual purpose pins.

2.3 LED INTERFACES

The DP83847 has 6 Light Emitting Diode (LED) outputs,

each capable to drive a maximum of 10 mA, to indicate the

status of Link, Transmit, Receive, Collision, Speed, and

Full/Half Duplex operation. The LED_CFG strap option is

used to configure the LED_FDPLX output for use as an

LED driver or more general purpose control pin. See the

table below:

The LED_FDPLX pin indicates the Half or Full Duplex con-

figuration of the port in both 10 Mb/s and 100 Mb/s opera-

tion. Since this pin is also used as the PHY address strap

option, the polarity of this indicator may be adjusted so that

in the “active” (FULL DUPLEX selected) state it drives

against the pullup/pulldown strap. In this configuration it is

suitable for use as an LED. When LED_CFG is high this

mode is selected and DsPHYTER automatically adjusts the

polarity of the output. If LED_CFG is low, the output drives

high to indicate the “active” state. In this configuration the

output is suitable for use as a control pin. The

LED_SPEED pin indicates 10 or 100 Mb/s data rate of the

port. The standard CMOS driver goes high when operating

in 100 Mb/s operation. Since this pin is not utilized as a

strap option, it is not affected by polarity adjustment.

The LED_GDLNK pin indicates the link status of the port.

Since this pin is also used as the PHY address strap

option, the polarity of this indicator is adjusted to be the

inverse of the strap value.

In 100BASE-T mode, link is established as a result of input

receive amplitude compliant with TP-PMD specifications

which will result in internal generation of signal detect.

10 Mb/s Link is established as a result of the reception of at

least seven consecutive normal Link Pulses or the recep-

tion of a valid 10BASE-T packet. This will cause the asser-

tion of GD_LINK. GD_LINK will deassert in accordance

with the Link Loss Timer as specified in IEEE 802.3.

The Collision LED indicates the presence of collision activ-

ity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit

has no meaning in Full Duplex operation and will be deas-

serted when the port is operating in Full Duplex. Since this

pin is also used as the PHY address strap option, the

polarity of this indicator is adjusted to be the inverse of the

strap value. In 10 Mb/s half duplex mode, the collision LED

is based on the COL signal. When in this mode, the user

should disable the Heartbeat (SQE) to avoid asserting the

COL LED during transmission. See Section 3.4.2 for more

information about the Heartbeat signal.

The LED_RX and LED_TX pins indicate the presence of

transmit and/or receive activity. Since these pins are also

used in PHY address strap options, the polarity is adjusted

to be the inverse of the respective strap values.

2.4 Half Duplex vs. Full Duplex

The DP83847 supports both half and full duplex operation

at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex is the standard, traditional mode of operation

which relies on the CSMA/CD protocol to handle collisions

and network access. In Half-Duplex mode, CRS responds

to both transmit and receive activity in order to maintain

compliance with IEEE 802.3 specification.

Since the DP83847 is designed to support simultaneous

transmit and receive activity it is capable of supporting full-

Figure 1. PHYAD Strapping and LED Loading Example

LED_FDPLX

LED_COL

LED_GDLNK

LED_TX

LED_RX

VCC

10kΩ

1kΩ

10kΩ

1kΩ

10kΩ

1kΩ

10kΩ

1kΩ

PHYAD0 = 1

PHYAD1 = 1

PHYAD2 = 0PHYAD3 = 0

PHYAD4= 0

10kΩ

Table 3. LED Mode Select

LED_CFG Mode Description

1 LED polarity adjusted

0 Duplex active-high

14 www.national.com

DP83847

duplex switched applications with a throughput of up to 200

Mb/s per port when operating in 100BASE-TX mode.

Because the CSMA/CD protocol does not apply to full-

duplex operation, the DP83847 disables its own internal

collision sensing and reporting functions and modifies the

behavior of Carrier Sense (CRS) such that it indicates only

receive activity. This allows a full-duplex capable MAC to

operate properly.

All modes of operation (100BASE-TX and 10BASE-T) can

run either half-duplex or full-duplex. Additionally, other than

CRS and Collision reporting, all remaining MII signaling

remains the same regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation

with the use of Fast Link Pulse code words can interpret

and configure to full-duplex operation, parallel detection

can not recognize the difference between full and half-

duplex from a fixed 10 Mb/s or 100 Mb/s link partner over

twisted pair. As specified in 802.3u, if a far-end link partner

is transmitting forced full duplex 100BASE-TX for example,

the parallel detection state machine in the receiving station

would be unable to detect the full duplex capability of the

far-end link partner and would negotiate to a half duplex

100BASE-TX configuration (same scenario for 10 Mb/s).

2.5 MII Isolate Mode

The DP83847 can be put into MII Isolate mode by writing to

bit 10 of the BMCR register. In addition, the MII isolate

mode can be selected by strapping in Physical Address 0.

It should be noted that selecting Physical Address 0 via an

MDIO write to PHYCTRL will not put the device in the MII

isolate mode.

When in the MII isolate mode, the DP83847 does not

respond to packet data present at TXD[3:0], TX_EN, and

TX_ER inputs and presents a high impedance on the

TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and

CRS outputs. The DP83847 will continue to respond to all

management transactions.

While in Isolate mode, the TD± outputs will not transmit

packet data but will continue to source 100BASE-TX

scrambled idles or 10BASE-T normal link pulses.

2.6 Loopback

The DP83847 includes a Loopback Test mode for facilitat-

ing system diagnostics. The Loopback mode is selected

through bit 14 (Loopback) of the Basic Mode Control Reg-

ister (BMCR). Writing 1 to this bit enables MII transmit data

to be routed to the MII receive outputs. Loopback status

may be checked in bit 3 of the PHY Status Register

(PHYSTS). While in Loopback mode the data will not be

transmitted onto the media in 100 Mb/s mode. To ensure

that the desired operating mode is maintained, Auto-Nego-

tiation should be disabled before selecting the Loopback

mode.

During 10BASE-T operation, in order to be standard com-

pliant, the loopback mode loops MII transmit data to the MII

receive data, however, Link Pulses are not looped back. In

100BASE-TX Loopback mode the data is routed through

the PCS and PMA layers into the PMD sublayer before it is

looped back. In addition to serving as a board diagnostic,

this mode serves as a functional verification of the device.

2.7 BIST

The DsPHYTER incorporates an internal Built-in Self Test

(BIST) circuit to accommodate in-circuit testing or diagnos-

tics. The BIST circuit can be utilized to test the integrity of

the transmit and receive data paths. BIST testing can be

performed with the part in the internal loopback mode or

externally looped back using a loopback cable fixture.

The BIST is implemented with independent transmit and

receive paths, with the transmit block generating a continu-

ous stream of a pseudo random sequence. The user can

select a 9 bit or 15 bit pseudo random sequence from the

PSR_15 bit in the PHY Control Register (PHYCTRL). The

looped back data is compared to the data generated by the

BIST Linear Feedback Shift Register (LFSR, which gener-

ates a pseudo random sequence) to determine the BIST

pass/fail status.

The pass/fail status of the BIST is stored in the BIST status

bit in the PHYCTRL register. The status bit defaults to 0

(BIST fail) and will transition on a successful comparison. If

an error (mis-compare) occurs, the status bit is latched and

is cleared upon a subsequent write to the Start/Stop bit.

Part #	DP83847ALQA56A
Description	IC ETHERNET TRANSCEIVER 56WQFN
Category	IC
Availability	In Stock
Qty	4

DP83847ALQA56A

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