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DP83847

1.2 10 Mb/s and 100 Mb/s PMD Interface

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O, PU/PD 26, 27, 29,

RECEIVE DATA: Nibble wide receive data (synchronous to cor-

responding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz

for 10BASE-T nibble mode). Data is driven on the falling edge of

RX_CLK. RXD[2] has an internal pull-down resistor. The remain-

ing RXD pins have pull-ups.

RX_ER/PAUSE_EN

S, O, PU 33 RECEIVE ERROR: Asserted high to indicate that an invalid sym-

bol has been detected within a received packet in 100BASE-TX

mode.

RX_DV O 31 RECEIVE DATA VALID: Asserted high to indicate that valid data

is present on the corresponding RXD[3:0] for nibble mode. Data

is driven on the falling edge of the corresponding RX_CLK.

Signal Name Type LLP Pin # Description

TD+, TD- O 10, 11 Differential common driver transmit output. These differential out-

puts are configurable to either 10BASE-T or 100BASE-TX signal-

ing.

The DP83847 will automatically configure the common driver out-

puts for the proper signal type as a result of either forced config-

uration or Auto-Negotiation.

RD-, RD+ I 6, 7 Differential receive input. These differential inputs can be config-

ured to accept either 100BASE-TX or 10BASE-T signaling.

The DP83847 will automatically configure the receive inputs to

accept the proper signal type as a result of either forced configu-

ration or Auto-Negotiation.

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DP83847

1.3 Clock Interface

1.4 Special Connections

1.5 LED Interface

Signal Name Type LLP Pin # Description

X1 I 49 REFERENCE CLOCK INPUT 25 MHz: This pin is the primary

clock reference input for the DP83847 and must be connected to

a 25 MHz 0.005% (±50 ppm) clock source. The DP83847 sup-

ports CMOS-level oscillator sources.

X2 O 48 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary

clock reference output.

Signal Name Type LLP Pin # Description

RBIAS I 3 Bias Resistor Connection. A 10.0 kΩ 1% resistor should be con-

nected from RBIAS to GND.

C1 O 42 Reference Bypass Regulator. Parallel caps, 10µ F (Tantalum pre-

ferred) and .1µF, should be placed close to C1 and connected to

GND. See Section 3.8 for proper placement.

RESERVED I/O 1, 2, 4, 5, 8,

9, 12, 13,

34, 44, 47,

50, 51, 52,

53, 54, 55,

RESERVED: These pins must be left unconnected

Signal Name Type LLP Pin # Description

LED_DPLX/PHYAD0 S, O 23 FULL DUPLEX LED STATUS: Indicates Full-Duplex status.

LED_COL/PHYAD1 S, O 22 COLLISION LED STATUS: Indicates Collision activity in Half Du-

plex mode.

LED_GDLNK/PHYAD2 S, O 21 GOOD LINK LED STATUS: Indicates Good Link Status for

10BASE-T and 100BASE-TX.

LED_TX/PHYAD3 S, O 20 TRANSMIT LED STATUS: Indicates transmit activity. LED is on

for activity, off for no activity.

LED_RX/PHYAD4 S, O 19 RECEIVE LED STATUS: Indicates receive activity. LED is on for

activity, off for no activity.

LED_SPEED O 18 SPEED LED STATUS: Indicates link speed; high for 100 Mb/s,

low for 10 Mb/s.

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DP83847

1.6 Strapping Options/Dual Purpose Pins

A 5 kΩ resistor should be used for pull-down or pull-up to

change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors, since the internal pull-up or pull down resis-

tors will set the default value. Please note that the

PHYAD[0:4] pins have no internal pull-ups or pull-downs

and they must be strapped. Since these pins may have

alternate functions after reset is deasserted, they should

not be connected directly to Vcc or GND.

Signal Name Type LLP Pin # Description

LED_DPLX/PHYAD0

LED_COL/PHYAD1

LED_GDLNK/PHYAD2

LED_TX/PHYAD3

LED_RX/PHYAD4

S, O 23

PHY ADDRESS [4:0]: The DP83847 provides five PHY address

pins, the state of which are latched into the PHYCTRL register at

system Hardware-Reset.

The DP83847 supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). PHY Address 0 puts the part

into the MII Isolate Mode. The MII isolate mode must be selected

by strapping Phy Address 0; changing to Address 0 by register

write will not put the Phy in the MII isolate mode.

The status of these pins are latched into the PHY Control Register

during Hardware-Reset. (Please note these pins have no internal

pull-up or pull-down resistors and they must be strapped high or

low using 5 kΩ resistors.)

AN_EN

AN_1

AN_0

S, O, PU 17

Auto-Negotiation Enable: When high enables Auto-Negotiation

with the capability set by ANO and AN1 pins. When low, puts the

part into Forced Mode with the capability set by AN0 and AN1

pins.

AN0 / AN1: These input pins control the forced or advertised op-

erating mode of the DP83847 according to the following table.

The value on these pins is set by connecting the input pins to

GND (0) or V

(1) through 5 kΩ resistors. These pins should

NEVER be connected directly to GND or V

CC.

The value set at this input is latched into the DP83847 at Hard-

ware-Reset.

The float/pull-down status of these pins are latched into the Basic

Mode Control Register and the Auto_Negotiation Advertisement

pins may switch to outputs so if pull-ups or pull-downs are imple-

mented, they should be pulled through a 5 kΩ resistor.

The default is 111 since these pins have pull-ups.

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex

0 0 1 10BASE-T, Full-Duplex

0 1 0 100BASE-TX, Half-Duplex

0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mode

1 0 0 10BASE-T, Half/Full-Duplex

1 0 1 100BASE-TX, Half/Full-Duplex

1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

Part #	DP83847ALQA56A
Description	IC ETHERNET TRANSCEIVER 56WQFN
Category	IC
Availability	In Stock
Qty	4

DP83847ALQA56A

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Technical Document