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DP83847ALQA56A

Part # DP83847ALQA56A
Description IC ETHERNET TRANSCEIVER 56WQFN
Category IC
Availability In Stock
Qty 4
Qty Price
1 + $3.29619
Manufacturer Available Qty
National Semiconductor Corp
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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DP83847
6.4.6 100BASE-TX Receive Packet Latency Timing
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion
of Carrier Sense.
Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
6.4.7 100BASE-TX Receive Packet Deassertion Timing
Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deasser-
tion of Carrier Sense.
Parameter Description Notes Min Typ Max Units
T4.6.1 Carrier Sense ON Delay 17.5 bit times
T4.6.2 Receive Data Latency 21 bit times
Parameter Description Notes Min Typ Max Units
T4.7.1 Carrier Sense OFF Delay 21.5 bit times
CRS
RXD[3:0]
RD±
RX_DV
RX_ER/RXD[4]
IDLE
Data
T4.6.1
T4.6.2
(J/K)
CRS
T4.7.1
RXD[3:0]
RX_DV
RX_ER/RXD[4]
RD±
DATA
IDLE
(T/R)
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DP83847
6.5 10 Mb/s Timing
6.5.1 10 Mb/s MII Transmit Timing
6.5.2 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK 25 ns
T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 5 ns
TX_CLK
TXD[3:0]
TX_EN
Valid Data
T5.1.1
T5.1.2
Parameter Description Notes Min Typ Max Units
T5.2.1 RX_CLK Duty Cycle 35 65 %
T5.2.2 RX_CLK to RXD[3:0], RX_DV 190 210 ns
RX_CLK
RXD[3:0]
Valid Data
T5.2.2
T5.2.1
RX_DV
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DP83847
6.5.3 10BASE-T Transmit Timing (Start of Packet)
6.5.4 10BASE-T Transmit Timing (End of Packet)
Parameter Description Notes Min Typ Max Units
T5.3.1 Transmit Enable Setup Time from the
Falling Edge of TX_CLK
25 ns
T5.3.2 Transmit Data Setup Time from the
Falling Edge of TX_CLK
25 ns
T5.3.3 Transmit Data Hold Time from the
Falling Edge of TX_CLK
5ns
T5.3.4 Transmit Output Delay from the
Falling Edge of TX_CLK
6.8 bit times
TX_CLK
TX_EN
TXD[0]
TPTD±
T5.3.1
T5.3.2
T5.3.3
T5.3.4
Parameter Description Notes Min Typ Max Units
T5.4.1 Transmit Enable Hold Time from the
Falling Edge of TX_CLK
5ns
T5.4.2 End of Packet High Time
(with ‘0’ ending bit)
250 ns
T5.4.3 End of Packet High Time
(with ‘1’ ending bit)
250 ns
TX_CLK
TX_EN
TPTD±
00
11
TPTD±
T5.4.2
T5.4.3
T5.4.1
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