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DP83847ALQA56A

Part # DP83847ALQA56A
Description IC ETHERNET TRANSCEIVER 56WQFN
Category IC
Availability In Stock
Qty 4
Qty Price
1 + $3.29619
Manufacturer Available Qty
National Semiconductor Corp
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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DP83847
Note: For Idd Measurements, outputs are not loaded.
V
TPTD_10
TD+/− 10M Transmit
Voltage
2.2 2.5 2.8 V
C
IN1
I CMOS Input
Capacitance
Parameter is not
100% tested
1pF
SD
THon
RD+/− 100BASE-TX
Signal detect turn-
on threshold
295 1000 mV diff
pk-pk
SD
THoff
RD+/− 100BASE-TX
Signal detect turn-
off threshold
200 mV diff
pk-pk
V
TH1
RD+/− 10BASE-T Re-
ceive Threshold
300 476 585 mV
I
dd100
Supply 100BASE-TX
(Full Duplex)
I
OUT
= 0 mA
See Note
106 mA
I
dd10
Supply 10BASE-T
(Full Duplex)
I
OUT
= 0 mA
See Note
90.5 mA
Symbol Pin Types Parameter Conditions Min Typ Max Units
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DP83847
6.1 Reset Timing
Note1: Software Reset should be initiated no sooner then 500 µs after power-up or the deassertion of hardware reset.
Note2: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Parameter Description Notes Min Typ Max Units
T1.0.1 Post RESET Stabilization time
prior to MDC preamble for reg-
ister accesses
MDIO is pulled high for 32-bit serial man-
agement initialization.
3 µs
T1.0.2 Hardware Configuration Latch-
in Time from the Deassertion of
RESET (either soft or hard)
Hardware Configuration Pins are de-
scribed in the Pin Description section.
3 µs
T1.0.3 Hardware Configuration pins
transition to output drivers
3.5 µs
T1.0.4 RESET pulse width X1 Clock must be stable for at min. of
160us during RESET pulse low time.
160 µs
V
CC
HARDWARE
RSTN
MDC
32 CLOCKS
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
INPUT
OUTPUT
T1.0.3
T1.0.2
T1.0.1
T1.0.4
X1 Clock
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DP83847
6.2 PGM Clock Timing
6.3 MII Serial Management Timing
Parameter Description Notes Min Typ Max Units
T2.0.1 TX_CLK Duty Cycle 35 65 %
TX_CLK
X1
T2.0.1
Parameter Description Notes Min Typ Max Units
T3.0.1 MDC to MDIO (Output) Delay Time 0 300 ns
T3.0.2 MDIO (Input) to MDC Setup Time 10 ns
T3.0.3 MDIO (Input) to MDC Hold Time 10 ns
T3.0.4 MDC Frequency 2.5 MHz
MDC
MDC
MDIO (output)
MDIO (input)
Valid Data
T3.0.1
T3.0.2 T3.0.3
T3.0.4
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