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DP83847

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired.

14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

13 MP 1, RW Message Page:

1 = Message Page.

0 = Unformatted Page.

12 ACK2 0, RW Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by the next page function to indicate that Lo-

cal Device has the ability to comply with the message received.

11 TOG_TX 0, RO Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word

was 0.

0 = Value of toggle bit in previously transmitted Link Code Word

was 1.

Toggle is used by the Arbitration function within Auto-Negotiation

to ensure synchronization with the Link Partner during Next Page

exchange. This bit shall always take the opposite value of the Tog-

gle bit in the previously exchanged Link Code Word.

10:0 CODE <000 0000 0001>,

This field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in annex 28C of IEEE

802.3u. Otherwise, the code shall be interpreted as an "Unformat-

ted Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined

in Annex 28C of IEEE 802.3u.

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DP83847

5.2 Extended Registers

This register provides a single location within the register set for quick access to commonly accessed information.

Table 16. PHY Status Register (PHYSTS), address 0x10

Bit Bit Name Default Description

15:14 RESERVED 0, RO RESERVED: Write ignored, read as 0.

13 Receive Error Latch 0, RO/LH Receive Error Latch:

This bit will be cleared upon a read of the RECR register.

1 = Receive error event has occurred since last read of RXERCNT

(address 0x15, Page 0).

0 = No receive error event has occurred.

12 Polarity Status 0, RO Polarity Status:

This bit is a duplication of bit 4 in the 10BTSCR register. This bit will

be cleared upon a read of the 10BTSCR register, but not upon a

read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

11 False Carrier Sense

Latch

0, RO/LH False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

1 = False Carrier event has occurred since last read of FCSCR (ad-

dress 0x14).

0 = No False Carrier event has occurred.

10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD.

9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD.

8 Page Received 0, RO Link Code Word Page Received:

This is a duplicate of the Page Received bit in the ANER register,

but this bit will not be cleared upon a read of the PHYSTS register.

1 = A new Link Code Word Page has been received. Cleared on

read of the ANER (address 0x06, bit 1).

0 = Link Code Word Page has not been received.

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DP83847

This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object

class of Clause 30 of the IEEE 802.3u specification.

7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.

6 Remote Fault 0, RO Remote Fault:

1 = Remote Fault condition detected (cleared on read of BMSR (ad-

dress 01h) register or by reset). Fault criteria: notification from Link

Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected.

5 Jabber Detect 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a duplicate of the Jabber Detect bit in the BMSR register,

except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected.

0 = No Jabber.

4 Auto-Neg Complete 0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation complete.

0 = Auto-Negotiation not complete.

3 Loopback Status 0, RO Loopback:

1 = Loopback enabled.

0 = Normal operation.

2 Duplex Status 0, RO Duplex:

This bit indicates duplex status and is determined from Auto-Nego-

tiation or Forced Modes.

1 = Full duplex mode.

0 = Half duplex mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

1 Speed Status 0, RO Speed10:

This bit indicates the status of the speed and is determined from

Auto-Negotiation or Forced Modes.

1 = 10 Mb/s mode.

0 = 100 Mb/s mode.

Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid link or if Auto-Negotiation is disabled and

there is a valid link.

0 Link Status 0, RO Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will no be cleared upon a read of the PHYSTS regis-

ter.

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0

7:0 FCSCNT[7:0] 0, RW / COR False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued)

Bit Bit Name Default Description

Part #	DP83847ALQA56A
Description	IC ETHERNET TRANSCEIVER 56WQFN
Category	IC
Availability	In Stock
Qty	4

DP83847ALQA56A

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