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DP83847

Table 7. Basic Mode Control Register (BMCR), Address 0x00

Bit Bit Name Default Description

15 Reset 0, RW/SC Reset:

1 = Initiate software Reset / Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset process is

complete. The configuration is re-strapped.

14 Loopback 0, RW Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MII transmit data to be routed to the MII receive

data path.

Setting this bit may cause the descrambler to lose synchronization and produce a

500 µs “dead time” before any valid data will appear at the MII receive outputs.

13 Speed Selection Strap, RW Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed to be se-

lected.

1 = 100 Mb/s.

0 = 10 Mb/s.

12 Auto-Negotiation

Enable

Strap, RW Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this

bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex

mode.

11 Power Down 0, RW Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is enabled during a

power down condition.

10 Isolate 0, RW Isolate:

1 = Isolates the Port from the MII with the exception of the serial management.

0 = Normal operation.

9 Restart Auto-

Negotiation

0, RW/SC Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-

Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and

will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-

clear. Operation of the Auto-Negotiation process is not affected by the manage-

ment entity clearing this bit.

0 = Normal operation.

8 Duplex Mode Strap, RW Duplex Mode:

When auto-negotiation is disabled writing to this bit allows the port Duplex capa-

bility to be selected.

1 = Full Duplex operation.

0 = Half Duplex operation.

7 Collision Test 0, RW Collision Test:

1 = Collision test enabled.

0 = Normal operation.

When set, this bit will cause the COL signal to be asserted in response to the as-

sertion of TX_EN within 512-bit times. The COL signal will be de-asserted within

4-bit times in response to the de-assertion of TX_EN.

6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.

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DP83847

Table 8. Basic Mode Status Register (BMSR), address 0x01

Bit Bit Name Default Description

15 100BASE-T4 0, RO/P 100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

14 100BASE-TX

Full Duplex

1, RO/P 100BASE-TX Full Duplex Capable:

1 = Device able to perform 100BASE-TX in full duplex mode.

13 100BASE-TX

Half Duplex

1, RO/P 100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

12 10BASE-T

Full Duplex

1, RO/P 10BASE-T Full Duplex Capable:

1 = Device able to perform 10BASE-T in full duplex mode.

11 10BASE-T

Half Duplex

1, RO/P 10BASE-T Half Duplex Capable:

1 = Device able to perform 10BASE-T in half duplex mode.

10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.

6MF Preamble

Suppression

1, RO/P Preamble suppression Capable:

1 = Device able to perform management transaction with preamble

suppressed, 32-bits of preamble needed only once after reset, invalid

opcode or invalid turnaround.

0 = Normal management operation.

5 Auto-Negotiation

Complete

0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation process complete.

0 = Auto-Negotiation process not complete.

4 Remote Fault 0, RO/LH Remote Fault:

1 = Remote Fault condition detected (cleared on read or by reset).

Fault criteria: Far End Fault Indication or notification from Link Part-

ner of Remote Fault.

0 = No remote fault condition detected.

3 Auto-Negotiation

Ability

1, RO/P Auto Negotiation Ability:

1 = Device is able to perform Auto-Negotiation.

0 = Device is not able to perform Auto-Negotiation.

2 Link Status 0, RO/LL Link Status:

1 = Valid link established (for either 10 or 100 Mb/s operation).

0 = Link not established.

The criteria for link validity is implementation specific. The occurrence

of a link failure condition will causes the Link Status bit to clear. Once

cleared, this bit may only be set by establishing a good link condition

and a read via the management interface.

1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.

1 = Jabber condition detected.

0 = No Jabber.

This bit is implemented with a latching function, such that the occur-

rence of a jabber condition causes it to set until it is cleared by a read

to this register by the management interface or by a reset.

0 Extended Capabili-

1, RO/P Extended Capability:

1 = Extended register capabilities.

0 = Basic register set capabilities only.

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DP83847

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83847. The Identifier consists of a

concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-

ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended

to support network management. National's IEEE assigned OUI is 080017h.

Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02

Bit Bit Name Default Description

15:0 OUI_MSB <0010 0000 0000

0000>, RO/P

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are

stored in bits 15 to 0 of this register. The most significant two bits

of the OUI are ignored (the IEEE standard refers to these as bits 1

and 2).

Table 10. PHY Identifier Register #2 (PHYIDR2), address 0x03

Bit Bit Name Default Description

15:10 OUI_LSB <01 0111>, RO/P OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of

this register respectively.

9:4 VNDR_MDL <00 0011>, RO/P Vendor Model Number:

The six bits of vendor model number are mapped to bits 9 to 4

(most significant bit to bit 9).

3:0 MDL_REV <0000>, RO/P Model Revision Number:

Four bits of the vendor model revision number are mapped to bits

3 to 0 (most significant bit to bit 3). This field will be incremented for

all major device changes.

Part #	DP83847ALQA56A
Description	IC ETHERNET TRANSCEIVER 56WQFN
Category	IC
Availability	In Stock
Qty	4

DP83847ALQA56A

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