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DP83847ALQA56A

Part # DP83847ALQA56A
Description IC ETHERNET TRANSCEIVER 56WQFN
Category IC
Availability In Stock
Qty 4
Qty Price
1 + $3.29619
Manufacturer Available Qty
National Semiconductor Corp
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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DP83847
Table of Content
1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . .6
1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Special Connections . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Strapping Options/Dual Purpose Pins . . . . . . . . . . 8
1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Power and Ground Pin . . . . . . . . . . . . . . . . . . . . . 9
1.9 Package Pin Assignments . . . . . . . . . . . . . . . . . . 10
2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 PHY Address and LEDs . . . . . . . . . . . . . . . . . . . 12
2.3 LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . 13
2.5 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . 16
3.3 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 20
3.4 10BASE-T TRANSCEIVER MODULE . . . . . . . . . 23
3.5 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . 26
3.8 Reference Bypass Couple . . . . . . . . . . . . . . . . . . 26
4.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . .37
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 MII Serial Management Timing . . . . . . . . . . . . . .47
6.4 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.7 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 60
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DP83847
Pin Layout
28 VDD
27 RXD_2
26 RXD_3
25 MDC
24 MDIO
23 LED_DPLX/PHYAD0
22 LED_COL/PHYAD1
21 LED_GDLNK/PHYAD2
20 LED_TX/PHYAD3
19 LED_RX/PHYAD4
18 LED_SPEED
17 AN_EN
16 AN_1
15 AN_0
COL 43
RESERVED 44
CRS/LED_CFG
45
RESET 46
RESERVED 47
X2 48
X1 49
RESERVED 50
RESERVED 51
RESERVED 52
RESERVED 53
RESERVED 54
RESERVED 55
VDD 56
42 C1
41 TXD_3
40 TXD_2
39 TXD_1
38 TXD_0
37 TX_EN
36 TX_CLK
35 TX_ER
34 RESERVED
33 RX_ER/PAUSE_EN
32 RX_CLK
31 RX_DV
30 RXD_0
29 RXD_1
RESERVED 1
RESERVED 2
RBIAS 3
RESERVED 4
RESERVED 5
RD - 6
RD+ 7
RESERVED 8
RESERVED 9
TD+ 10
TD- 11
RESERVED 12
RESERVED 13
VDD 14
Top View
Leadless Leadframe Package (LLP)
Order Number DP83847ALQA56A
NS Package Number LQA-56A
65 Gnd
57
58
63
64
61
62
59
60
Note 1: Pins 57 to 65 required soldering care. Check Package Instruction, AN-1187, for details.
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DP83847
1.0 Pin Descriptions
The DP83847 pins are classified into the following interface
categories (each interface is described in the sections that
follow):
MII Interface
10/100 Mb/s PMD Interface
Clock Interface
Special Connect Pins
LED Interface
Strapping Options/Dual Function pins
—Reset
Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
All DP83847 signal pins are I/O cells regardless of the par-
ticular use. Below definitions define the functionality of the
I/O cells for each pin.
1.1 MII Interface
Type: I Inputs
Type: O Outputs
Type: I/O Input/Output
Type OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins except PHY-
AD[0:4] have internal pull-ups or pull-
downs. If the default strap value is needed
to be changed then an external 5 k resistor
should be used. Please see Table 1.6 on
page 8 for details.)
Signal Name Type LLP Pin # Description
MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO I/O, OD 24 MANAGEMENT DATA I/O: Bi-directional management instruc-
tion/data signal that may be sourced by the station management
entity or the PHY. This pin requires a 1.5 k pullup resistor.
CRS/LED_CFG
O, S 45 CARRIER SENSE: Asserted high to indicate the presence of car-
rier due to receive or transmit activity in 10BASE-T or 100BASE-
TX Half Duplex Modes, while in full duplex mode carrier sense is
asserted to indicate the presence of carrier due only to receive ac-
tivity.
COL O 43 COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in
10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled this
pin are also asserted for a duration of approximately 1µs at the
end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this sig-
nal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.
TX_CLK O 36 TRANSMIT CLOCK: 25 MHz Transmit clock outputs in
100BASE-TX mode or 2.5 MHz in 10BASE-T mode derived from
the 25 MHz reference clock.
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
I 41, 40, 39,
38
TRANSMIT DATA: Transmit data MII input pins that accept nib-
ble data synchronous to the TX_CLK (2.5 MHz in 10BASE-T
Mode or 25 MHz in 100BASE-TX mode).
TX_EN I 37 TRANSMIT ENABLE: Active high input indicates the presence of
valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10
Mb/s nibble mode.
TX_ER I 35 TRANSMIT ERROR: In 100MB/s mode, when this signal is high
and the corresponding TX_EN is active the HALT symbol is sub-
stituted for data.
In 10 Mb/s this input is ignored.
RX_CLK O, PU 32 RECEIVE CLOCK: Provides the 25 MHz recovered receive
clocks for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble
mode.
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