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MSP430F2274TRHAT

Part # MSP430F2274TRHAT
Description MCU 16-bit MSP430 MSP430 RISC32KB Flash 2.5V/3.3V 40-Pin
Category IC
Availability In Stock
Qty 214
Qty Price
1 - 44 $3.57032
45 - 89 $2.84003
90 - 134 $2.67774
135 - 179 $2.48841
180 + $2.21793
Manufacturer Available Qty
Texas Instruments
Date Code: 0706
  • Shipping Freelance Stock: 198
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Texas Instruments
Date Code: 0712
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
16
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
memory organization
MSP430F223x MSP430F225x MSP430F227x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0FFFFh−0FFC0h
0FFFFh−0E000h
16KB Flash
0FFFFh−0FFC0h
0FFFFh−0C000h
32KB Flash
0FFFFh−0FFC0h
0FFFFh−08000h
Information memory Size
Flash
256 Byte
010FFh−01000h
256 Byte
010FFh−01000h
256 Byte
010FFh−01000h
Boot memory Size
ROM
1KB
0FFFh−0C00h
1KB
0FFFh−0C00h
1KB
0FFFh−0C00h
RAM Size 512 Byte
03FFh−0200h
512 Byte
03FFh−0200h
1KB
05FFh−0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh−0100h
0FFh−010h
0Fh−00h
01FFh−0100h
0FFh−010h
0Fh−00h
01FFh−0100h
0FFh−010h
0Fh−00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the application report, Features of the
MSP430 Bootstrap Loader, TI literature number SLAA089.
BSL Function DA Package Pins RHA Package Pins
Data transmit 32 - P1.1 30 - P1.1
Data receive 10 - P2.2 8 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0−n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO),
and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 μs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very
low power LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency Calibration Register Size Address
1 MHz
CALBC1_1MHZ byte
010FFh
CALDCO_1MHZ byte
010FEh
8 MHz
CALBC1_8MHZ byte
010FDh
CALDCO_8MHZ byte
010FCh
12 MHz
CALBC1_12MHZ byte
010FBh
CALDCO_12MHZ byte
010FAh
16 MHz
CALBC1_16MHZ byte
010F9h
CALDCO_16MHZ byte
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown resistor.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
18
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
Module
Block
Module
Output Signal
Output
Pin Number
DA RHA DA RHA
31 - P1.0 29 - P1.0 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
9 - P2.1 7 - P2.1 TAINCLK INCLK
32 - P1.1 30 - P1.1 TA0 CCI0A
32 - P1.1 30 - P1.1
10 - P2.2 8 - P2.2 TA0 CCI0B
CCR0
TA0
10 - P2.2 8 - P2.2
V
SS
GND
CCR0 TA0
36 - P1.5 34 - P1.5
V
CC
V
CC
33 - P1.2 31 - P1.2 TA1 CCI1A
33 - P1.2 31 - P1.2
29 - P2.3 27 - P2.3 TA1 CCI1B
CCR1
TA1
29 - P2.3 27 - P2.3
V
SS
GND
CCR1 TA1
37 - P1.6 35 - P1.6
V
CC
V
CC
34 - P1.3 32 - P1.3 TA2 CCI2A
34 - P1.3 32 - P1.3
ACLK (internal) CCI2B
CCR2
TA2
30 - P2.4 28 - P2.4
V
SS
GND
CCR2 TA2
38 - P1.7 36 - P1.7
V
CC
V
CC
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