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MSP430F2274TRHAT

Part # MSP430F2274TRHAT
Description MCU 16-bit MSP430 MSP430 RISC32KB Flash 2.5V/3.3V 40-Pin
Category IC
Availability In Stock
Qty 214
Qty Price
1 - 44 $3.57032
45 - 89 $2.84003
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135 - 179 $2.48841
180 + $2.21793
Manufacturer Available Qty
Texas Instruments
Date Code: 0706
  • Shipping Freelance Stock: 198
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Texas Instruments
Date Code: 0712
  • Shipping Freelance Stock: 16
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset 0FFFEh 31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh 30
Timer_B3 TBCCR0 CCIFG (see Note 3) maskable 0FFFAh 29
Timer_B3
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 2 and 3)
maskable 0FFF8h 28
0FFF6h 27
Watchdog Timer WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
Timer_A3
TACCR1 CCIFG.
TACCR2 CCIFG
TAIFG (see Notes 2 and 3)
maskable 0FFF0h 24
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG
(see Notes 2)
maskable 0FFEEh 23
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG
(see Notes 2)
maskable 0FFECh 22
ADC10 ADC10IFG (see Note 3) maskable 0FFEAh 21
0FFE8h 20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 and 3)
maskable 0FFE6h 19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
(see Note 5) 0FFDEh 15
(see Note 6) 0FFDCh ... 0FFC0h 14 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module.
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
5. This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address 7 6 5 43210
00h
ACCVIE NMIIE OFIE WDTIE
rw−0 rw−0 rw−0 rw−0
WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured
in interval timer mode.
OFIE Oscillator fault enable
NMIIE (Non)-maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address 7 6 5 43210
01h
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw−0 rw−0 rw−0 rw−0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
interrupt flag register 1 and 2
Address 7 6 5 43210
02h
NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw−0 rw−(0) rw−(1) rw−1 rw−(0)
WDTIFG Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
CC
power up.
PORIFG Power-On interrupt flag. Set on V
CC
power up.
NMIIFG Set via RST/NMI-pin
Address 7 6 5 43210
03h
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw−1 rw−0 rw−1 rw−0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
rw-(0,1):
SFR bit is not present in device.
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