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MSP430F2274TRHAT

Part # MSP430F2274TRHAT
Description MCU 16-bit MSP430 MSP430 RISC32KB Flash 2.5V/3.3V 40-Pin
Category IC
Availability In Stock
Qty 214
Qty Price
1 - 44 $3.57032
45 - 89 $2.84003
90 - 134 $2.67774
135 - 179 $2.48841
180 + $2.21793
Manufacturer Available Qty
Texas Instruments
Date Code: 0706
  • Shipping Freelance Stock: 198
    Ships Immediately
Texas Instruments
Date Code: 0712
  • Shipping Freelance Stock: 16
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
55
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
CC(PGM/
ERASE)
Program and erase supply voltage 2.2 3.6 V
f
FTG
Flash timing generator frequency 257 476 kHz
I
PGM
Supply current from V
CC
during program 2.2 V/3.6 V 1 5 mA
I
ERASE
Supply current from V
CC
during erase 2.2 V/3.6 V 1 7 mA
t
CPT
Cumulative program time (see Note 1) 2.2 V/3.6 V 10 ms
t
CMErase
Cumulative mass erase time 2.2 V/3.6 V 20 ms
Program/erase endurance 10
4
10
5
cycles
t
Retention
Data retention duration T
J
= 25°C 100 years
t
Word
Word or byte program time see Note 2 30
t
Block,
0
Block program time for first byte or word see Note 2 25
t
Block,
1-63
Block program time for each additional byte or word see Note 2 18
t
t
Block,
End
Block program end-sequence wait time see Note 2 6
t
FTG
t
Mass
Erase
Mass erase time see Note 2 10593
t
Seg
Erase
Segment erase time see Note 2 4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the flash controller’s state machine (t
FTG
= 1/f
FTG
).
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(RAMh)
RAM retention supply voltage (see Note 1) CPU halted 1.6 V
NOTE 1: This parameter defines the minimum supply voltage V
CC
when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
56
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire Interface
PARAMETER
TEST
CONDITIONS
VCC MIN TYP MAX UNIT
f
SBW
Spy-Bi-Wire input frequency 2.2 V / 3 V 0 20 MHz
t
SBW,Low
Spy-Bi-Wire low clock pulse length 2.2 V / 3 V 0.025 15 μs
t
SBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge,
see Note 1)
2.2 V/ 3 V 1 μs
t
SBW,Ret
Spy-Bi-Wire return to normal operation time 2.2 V/ 3 V 15 100 μs
f
TCK input frequency (see Note 2)
2.2 V 0 5
MHz
f
TCK
TCK input frequency (see Note 2)
3 V 0 10
MHz
R
Internal
Internal pull-down resistance on TEST 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
SBW,En
time after pulling the TEST/SBWCLK pin high
before applying the first SBWCLK clock edge.
2. f
TCK
may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (see Note 1)
PARAMETER
TEST
CONDITIONS
VCC MIN TYP MAX UNIT
V
CC(FB)
Supply voltage during fuse-blow condition T
A
= 25°C 2.5 V
V
FB
Voltage level on TEST for fuse blow 6 7 V
I
FB
Supply current into TEST during fuse blow 100 mA
t
FB
Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible, and it is switched to bypass mode.
MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504B − JULY 2006 − REVISED JULY 2007
57
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
0
DVSS
DVCC
P1REN.x
Pad Logic
1
Port P1 (P1.0 to P1.3) pin functions
PIN NAME (P1 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X FUNCTION
P1DIR.x P1SEL.x
P1.0/ 0 P1.0† (I/O) I: 0; O: 1 0
TACLK/ADC10CLk
Timer_A3.TACLK 0 1
ADC10CLK 1 1
P1.1/TA0 1 P1.1† (I/O) I: 0; O: 1 0
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.2/TA1 2 P1.2† (I/O) I: 0; O: 1 0
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.3/TA2 3 P1.3† (I/O) I: 0; O: 1 0
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable
2. X: Don’t care
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