October 2004 21 M9999-102604
KS8695X Micrel
Reserved Pins
Pin Name I/O Type(
1)
Description
84 TEST3 NC The Reserved Pins serve as no connect in order to ensure correct operation of
the device. DO NOT connect any signal to these pins.
130 TEST4 NC No connect.
131 TEST5 NC No connect.
132 TEST6 NC No connect.
133 TEST7 NC No connect.
134 TEST8 NC No connect.
135 TEST9 NC No connect.
136 TEST10 NC No connect.
139 TEST11 NC No connect.
140 TEST12 NC No connect.
141 TEST13 NC No connect.
142 TEST14 NC No connect.
143 TEST15 NC No connect.
144 TEST16 NC No connect.
145 TEST17 NC No connect.
146 TEST18 NC No connect.
147 TEST19 NC No connect.
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
24 SDICLK I SDRAM Clock In: SDRAM clock input for the SDRAM memory controller interface.
23 SDOCLK O System/SDRAM Clock Out: Output of the internal system clock, it is also used as the
clock signal for SDRAM interface.
205 ADDR21/BA1 O Address Bit 21/Bank Address Input 1: Address bit 21 for asynchronous accesses.
Bank Address Input bit 1 for SDRAM accesses.
206 ADDR20/BA0 O Address Bit 20/Bank Address Input 0: Address bit 20 for asynchronous accesses.
Bank Address Input bit 0 for SDRAM accesses.
198 ADDR[19] O Address Bus: The 22-bit address bus (including ADDR[21:20] above) covers 4M word
199 ADDR[18] memory space shared by ROM/SRAM/FLASH, SDRAM, and external I/O banks.
200 ADDR[17] During the SDRAM cycles, the internal address bus is used to generate RAS and
201 ADDR[16] CAS addresses for the SDRAM. The number of column address bits in the SDRAM
202 ADDR[15] banks can be programmed from 8 to 11 bits via the SDRAM control registers.
203 ADDR[14] ADDR[12:0] are the SDRAM address, and ADDR[21:20] are the SDRAM bank
204 ADDR[13] address. During other cycles, the ADDR[21:0] is the byte address of the data transfer.
207 ADDR[12] Note: The address pinout non-sequential by design. It is optimized for board level
208 ADDR[11] connections to SDRAM.
3 ADDR[10]
4 ADDR[9]
5 ADDR[8]
6 ADDR[7]
7 ADDR[6]
8 ADDR[5]
9 ADDR[4]
10 ADDR[3]
13 ADDR[2]
14 ADDR[1]
15 ADDR[0]
Note:
1. I = Input.
O = Output.
NC = No connect.
For SDRAM and ROM/SRAM/Flash, connect ADDR[0] to A0 on the memory,
ADDR[1] to A1 on the memory, and so forth. Address bit mapping for 8-bit,
16-bit, 32-bit access.
For external I/O devices, the system designer must connect address lines
conventionally for 8-bit, 16-bit, and 32-bit access.
