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KS8695P

Part # KS8695P
Description IC SWITCH 10/100 3PORT 289PBGA
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

KS8695P
Integrated Multi-Port PCI Gateway Solution
Rev. 1.5
XceleRouter is a trademark of Micrel, Inc. AMD is a registered trademark of Advanced Micro Devices, Inc. ARM is a trademark of Advanced RISC Machines Ltd.
Intel is a registered trademark of Intel Corporation. WinCE is a registered trademark of Microsoft Corporation.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2006
M9999-051806
General Description
The CENTAUR KS8695P, Multi-Port PCI Gateway
Solution, delivers a new level of networking integration,
performance, and overall BOM cost savings, enabling
original equipment manufacturers (OEMs) to provide
customers with feature-rich, low-cost solutions for the
residential gateway and small office environment.
Integration of a PCI arbiter supporting three external
masters.
Allows incorporation of a variety of productivity
enhancing system interfaces, including the expanding
802.11 a/g/b wireless LAN.
High-performance ARM™ CPU (ARM9) with 8KB
I-cache, 8KB D-cache, and a memory management unit
(MMU) for Linux and WinCE
®
support.
XceleRouter™ technology to accelerate packet
processing.
Proven wire-speed switching technology that includes
802.1Q tag-based VLAN and quality of service (QoS)
support.
Five patented mixed-signal, low-powered Fast Ethernet
transceivers with corresponding media access control
(MAC) units.
Advanced memory interface with programmable 8/16/32-
bit data and 22-bit address bus with up to 64MB of total
memory space for Flash, ROM, SRAM, SDRAM, and
external peripherals.
Functional Diagram
Supports
up to
3 External
PCI Masters
Micrel, Inc. KS8695P
May 2006
2
M9999-051806
Features
The CENTAUR KS8695P featuring XceleRouter
technology is a single-chip, multi-port PCI "gateway-on-
a-chip" with all the key components integrated for a high-
performance and low-cost broadband gateway.
ARM9 High-Performance CPU Core
ARM9 core at 166MHz
8KB I-cache and 8KB D-cache
Memory management unit (MMU) for Linux and WinCE
32-bit ARM and 16-bit thumb instruction sets for
smaller memory footprints
33MHz 32-Bit PCI Interface
Version PCI 2.1
Supports bus mastership or guest-mode
Supports normal and memory-mapped I/O
Support for miniPCI and cardbus peripherals
Integrated Ethernet Transceivers and Switch Engine
– Five 10/100 Ethernet transceivers and ve MACs (1P
for WAN interface, 4P for LAN switching)
– 100BASE-FX mode option on the WAN port and one
LAN port
Automatic MDI/MDI-X crossover on all ports
Wire-speed, non-blocking switch
802.1Q tag-based VLAN (16 VLANs, full range VID)
Port-based VLAN
QoS/CoS packet prioritization support: per port, 802.1p,
and DiffServ-based
64KB on-chip frame buffer SRAM
VLAN ID and 802.1P tag/untag option per port
802.1D Spanning Tree Protocol support
Programmable rate-limiting per port: 0Mbps to
100Mbps, ingress and egress, rate options for high and
low priority
Extensive MIB counter management support
IGMP snooping for multicast packet ltering
Dedicated 1K entry look-up engine
– Port mirroring/monitoring/snifng
Broadcast and multicast storm protection with % control
global and per port basis
Full- and half-duplex ow control
XceleRouter Technology
TCP/UDP/IP packet header checksum generation to
ofoad CPU tasks
– IPv4 packet ltering on checksum errors
Automatic error packet discard
DMA engine with burst-mode support for efcient
WAN/LAN data transfers
FIFOs for back-to-back packet transfers
Memory and External I/O Interfaces
8/16/32-bit wide shared data path for Flash, ROM,
SRAM, SDRAM, and external I/O
Total memory space up to 64MB
– Intel
®
/AMD
®
-type Flash support
Peripheral Support
8/16/32-bit external I/O interface supporting PCMCIA or
generic CPU/DSP host I/F
Sixteen general purpose input/output (GPIO)
Two 32-bit timer counters (one watchdog)
– Interrupt controller
System Design
Up to 166MHz CPU and 125MHz bus speed
289 PBGA package (19mm x 19mm) saving board real
estate
Two power supplies: 1.8V core and Ethernet RX
supply, 3.3V I/O and Ethernet TX supply
Built-in LED controls
Debugging
ARM9 JTAG debug interface
UART for console port or modem back-up
Power Management
CPU and system clock speed step-down options
Low-power Ethernet transceivers
Per port power-down and Ethernet transmit disable
Reference Hardware and Software Evaluation Kit
Hardware evaluation board (passes class B EMI)
Board support package including rmware source
codes, Linux kernel, and software stacks
Complete hardware and software reference designs
available
Applications
Multi-port wireless VoIP gateway
Wireless mesh network node
RG + combo 802.11 a/b/g/n access point
Multimedia gateway
Digital audio access point
Network storage element
Multi-port broadband gateway
Multi-port rewall and VPN appliances
Combination wireless and wireline gateway
Fiber-to-the-home managed CPE
Micrel, Inc. KS8695P
May 2006
3
M9999-051806
Ordering Information
Commercial Part Number
Standard Pb (lead)-Free
Temperature
Range
Package
KS8695P KSZ8695P 0° to +70°C 289-Pin PBGA
Industrial Part Number
Standard Pb (lead)-Free
Temperature
Range
Package
KS8695PI KSZ8695PI –40° to +85°C 289-Pin PBGA
Revision History
Revision Date Summary of Changes
0.9 05/13/03 Created.
0.91 06/04/03 Corrected WRSTPLS sets WRSTO to active low when ‘1’, and active high when ‘0’.
0.92 06/10/03
Changed pin A1 to GND. Changed pin E3, H7, J7, K7, L7 to AGND. Changed Figure 5 WRSTPLS to
pull up.
0.93 07/11/03 Removed PCI 2.2 compliance. Removed TM from Centaur. Added LANFXSD1 signal description.
0.94 07/17/03 Updated DC Electrical Characteristics.
0.95 08/11/03
Added addressing description to memory controller and address pin description Table 11. Changed
PRSTN to input in Table 10.
1.0 09/02/03
Changed Figure 1. Removed old register address tables and replaced with Figure 11. Added Memory
Interface examples, Figures 7,8, and 9. Added memory interface description, section 2.5.
1.1 09/29/03 Changed Figure 2.
1.2 08/04/04 Transferred to Micrel format and updated System Clock.
1.3 01/27/05 Added recommended reset circuit.
1.4 08/18/05 Added wireless applications. Added Pb-Free and industrial specication. Edits to Pin Description Table.
1.5 05/18/06 Added Pb-Free option for industrial specication.
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