DS17285/DS17287
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The DS17285/DS17287 power-control circuitry allows the system to be powered on by an external
stimulus such as a keyboard or by a time-and-date (wake-up) alarm. The PWR output pin is triggered by
one or either of these events, and is used to turn on an external power supply. The PWR pin is under
software control, so that when a task is complete, the system power can then be shut down.
The DS17285 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS17287 incorporates the DS17285 chip, a 32.768kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of V
CC
is guaranteed.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS17285/DS17287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, V
CC
– DC power is provided to the device on these pins. V
CC
is the +3V or +5V input.
SQW – Square-Wave Output. The SQW pin provides a 32kHz square-wave output, t
REC
, after a power-
up condition has been detected. This condition sets the following bits, enabling the 32kHz output;
DV1 = 1, and E32k = 1. A square wave is output on this pin if either SQWE = 1 or E32k = 1. If E32k = 1,
then 32kHz is output regardless of the other control bits. If E32k = 0, then the output frequency is
dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by
programming Register A, as shown in Table 2. The SQW signal can be turned on and off using the
SQWE bit in register B or the E32k bit in extended register 4Bh. A 32kHz SQW signal is output when the
enable 32kHz (E32k) bit in extended register 4Bh is a logic 1 and V
CC
is above V
PF
. A 32kHz square
wave is also available when V
CC
is less than V
PF
if E32k = 1, ABE = 1, and voltage is applied to the
V
BAUX
pin.
AD0 to AD7 – Multiplexed Bidirectional Address/Data Bus. Multiplexed buses save pins because
address information time and data information time share the same signal paths. The addresses are
present during the first portion of the bus cycle and the same pins and signal paths are used for data in the
second portion of the cycle. Address/data multiplexing does not slow the access time of the DS17285
since the bus change from address to data occurs during the internal RAM access time. Addresses must
be valid prior to the latter portion of ALE, at which time the DS17285/DS17287 latches the address.
Valid write data must be present and held stable during the latter portion of the WR pulse. In a read cycle
the DS17285/DS17287 outputs 8 bits of data during the latter portion of the
RD pulse. The read cycle is
terminated and the bus returns to a high impedance state as
RD transitions high. The address/data bus
also serves as a bidirectional data path for the external extended RAM.
ALE – RTC Address Strobe Input; Active High. A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS17285/DS17287.
RD –RTC Read Input; Active Low. RD identifies the time period when the DS17285/DS17287 drives
the bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
