CY7C027/028
CY7C037/038
Document #: 38-06042 Rev. *A Page 10 of 19
Notes:
28. R/W
must be HIGH during all address transitions.
29. A write occurs during the overlap (t
SCE
or t
PWE
) of a LOW CE or SEM and a LOW UB or LB.
30. t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
31. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on
the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
PWE
.
32. To access RAM, CE
= V
IL
, SEM = V
IH
.
33. To access upper byte, CE
= V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE
= V
IL
, LB = V
IL
, SEM = V
IH
.
34. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE
or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Write Cycle No. 1: R/W Controlled Timing
[28, 29, 30, 31]
[34]
[34]
[31]
[32,33]
NOTE 35
NOTE 35
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Write Cycle No. 2: CE Controlled Timing
[28, 29, 30, 34, 35]
[32,33]
