CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. ** Page 2 of 19
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided, permit-
ting independent, simultaneous access for reads and writes to
any location in memory.
[6]
Registers on control, address, and
data lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid t
CD2
= 6.5 ns
[1, 2]
(pipelined). Flow-through
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available t
CD1
= 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT
/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW
to HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS
). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH tran-
sition of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN
is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter Reset (CNTRST
) is
used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
Notes:
6. When writing simultaneously to the same location, the final value cannot be guaranteed.
7. This pin is NC for CY7C09269V.
8. This pin is NC for CY7C09269V and CY7C09279V.
9. For CY7C09269V and CY7C09279V, pin #18 connected to V
CC
is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5V x16 flow-through device.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
ADSR
A0R
A1R
A0L
A2L
CLKR
CNTENR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C09289V (64K x 16)
100-Pin TQFP (Top View)
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[
8]
[
9]
[
9]
[
7]
[
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