C8051F320/1

28 Rev. 1.4

3. Global Electrical Characteristics

Table 3.1. Global Electrical Characteristics

–40 to +85 °C, 25 MHz system clock unless otherwise noted.

Parameter Conditions Min Typ Max Units

Digital Supply Voltage

RST

1,2

3.0 3.6 V

Digital Supply RAM Data

Retentio

n Voltage

- 1.5 — V

SYSCLK (System Clock)

0 — 25 MHz

SYSH

(SYSCLK High Time)

18 — — ns

SYSL

(SYSCLK Low Time)

18 — — ns

Specificed Operating Tem-

perature Range

–40 — +85 °C

Digital Supply Current - CPU Active (Normal Mode, fetching instructions from Flash)

IDD

= 3.6 V; F = 25 MHz — 12.3 13.6 mA

= 3.3 V, F = 24 MHz — 10.6 11.5 mA

= 3.3 V, F = 6 MHz — 3.2 — mA

= 3.3 V, F = 32 kHz — 38 — uA

= 3.0 V, F = 24 MHz — 9.0 9.8 mA

= 3.0 V, F = 6 MHz — 2.7 — mA

= 3.0 V, F = 32 kHz — 32 — uA

IDD Supply Sensitivity

F = 24 MHz — 0.66 — %/V

F = 6 MHz — 0.63 — %/V

IDD Frequency Sensitivity

4,5

= 3.0 V, F < 15 MHz, T = 25 °C — 0.45 — mA/MHz

= 3.0 V, F > 15 MHz, T = 25 °C — 0.26 — mA/MHz

= 3.3 V, F < 15 MHz, T = 25 °C — 0.53 — mA/MHz

= 3.3 V, F > 15 MHz, T = 25 °C — 0.29 — mA/MHz

Digital Supply Current - CPU and USB Active (USB Transceiver Enabled and Connected to PC)

IDD

= 3.3 V, F = 24 MHz, Full Speed — 16.8 — mA

= 3.0 V, F = 24 MHz, Full Speed — 14.4 — mA

= 3.3 V, F = 6 MHz, Low Speed — 7.2 — mA

= 3.0 V, F = 6 MHz, Low Speed — 6.0 — mA

Digital Supply Current - CPU Inactive (Idle Mode, not fetching instructions from Flash)

Idle IDD

= 3.6 V; F = 25 Mhz — 5.8 6.5 mA

= 3.3 V, F = 24 MHz — 5.2 5.9 mA

= 3.3 V, F = 6 MHz — 1.7 — mA

= 3.3 V, F = 32 kHz — 14 — uA

= 3.0 V, F = 24 MHz — 4.6 5.2 mA

= 3.0 V, F = 6 MHz — 1.5 — mA

= 3.0 V, F = 32 kHz — 11 — uA

Rev. 1.4 29

C8051F320/1

Idle IDD Supply Sensitivity

F = 24 MHz — 0.47 — %/V

F = 6 MHz — 0.50 — %/V

Idle IDD Frequency 

Sensitivity

4,6

= 3.0 V, F < 1 MHz, T = 25 °C — 0.25 — mA/MHz

= 3.0 V, F > 1 MHz, T = 25 °C — 0.17 — mA/MHz

= 3.3 V, F < 1 MHz, T = 25 °C — 0.29 — mA/MHz

= 3.3 V, F > 1 MHz, T = 25 °C — 0.20 — mA/MHz

Digital Supply Current 

(Stop Mode)

Oscillator not running,

Monitor disabled

— <0.1 — µA

Notes:

1. Given in Table 10.1, “Reset Electrical Characteristics,” on page 105.

2. USB requires a minimum supply voltage of 3.0 V.

3. SYSCLK must

be at least 32 kHz to enable debugging.

4. Based on device characterization data; Not production tested.

5. IDD can be estimated for frequencies < 15 MHz by simply multiplying the frequency of interest by the

frequency sensitivity number for that range. When using these numbers to estimate IDD for >15 MHz, the

estimate

should be the current at 24 MHz minus the difference in current indicated by the frequency sensitivity

number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 9.0 mA – (24 MHz –

20 MHz) x 0.26 mA/MHz = 7.96 mA.

6. Idle IDD can be estimated for frequencies

< 1 MHz by simply multiplying the frequency of interest by the

frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the

estimate should be the current at 24 MHz minus the difference in current indica

ted by the frequency sensitivity

number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.6 mA – (24 MHz –

5 MHz) x 0.17 mA/MHz = 1.37 mA.

Table 3.2. Index to Electrical Characteristics Tables

Peripheral Electrical Characteristics Page #

ADC0 Electrical Characteristics

Voltage Reference Electrical Characteristics

Comparator Electrical Characteristics

Voltage Regulator Electrical Characteristics

Reset Electrical Characteristics

105

Flash Electrical Characteristics

107

Internal Oscillator Electrical Characteristics

125

Port I/O DC Electrical Characteristics

138

Table 3.1. Global Electrical Characteristics (Continued)

–40 to +85 °C, 25 MHz system clock unless otherwise noted.

Parameter Conditions Min Typ Max Units

C8051F320/1

30 Rev. 1.4

4. Pinout and Package Definitions

Table 4.1. Pin Definitions for the C8051F320/1

Name

Pin Numbers

Type Description

‘F320 ‘F321

VDD 6 6

Power In

Power

Out

2.7-3.6 V Power Supply V

oltage Input.

3.3 V Voltage Regulator Output. See Section 8.

GND 3 3 Ground.

/RST/

C2CK

9 9

D I/O

Device Reset. Open-drain output of internal POR or VDD

mon

itor. An external source can initiate a system reset by

driving this pin low for at least 15 µs. See Section 10.

Clock signal for the C2 Debug Interface.

P3.0/

C2D

10 10

D I/O

Port 3.0. See Section 14 for a complete description.

Bi-directional data signal for the C2 Debug Interface.

REGIN

7 7

Power In 5 V Regulator Input. This pin is the input to the on-chip volt-

age regulator.

VBUS 8 8 D In

VBUS Sense Input. This pin should be connected to the

VBUS signal

of a USB network. A 5 V signal on this pin indi-

cates a USB network connection.

D+ 4 4 D I/O USB D+.

D- 5 5 D I/O USB D–.

P0.0 2 2 D I/O Port 0.0. See Section 14 for a complete description of Port 0.

P0.1 1 1 D I/O Port 0.1.

P0.2/

XTAL1

32 28

D I/O

A In

Port 0.2.

External Clock Input. This pin is the extern

al oscillator return

for a crystal or resonator. See Section 13.

P0.3/

XTAL2

31 27

D I/O

A I/O or

D In

Port 0.3.

External Clock Output. This pin is the

excitation driver for an

external crystal or resonator, or an external clock input for

CMOS, capacitor, or RC oscillator configurations. See Sec-

tion 13.

P0.4 30 26 D I/O Port 0.4.

P0.5 29 25 D I/O Port 0.5.

P0.6/

CNVSTR

28 24

Port 0.6.

ADC0 External Convert Start Input. See Section 5.

P0.7/

VREF

27 23

D I/O

A I/O

Port 0.7.

External VREF input or

output. See Section 6.

P1.0 26 22

D I/O or

A In

Port 1.0. See Section 14 for a complete description of Port 1.

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document