Rev. 1.4 23
C8051F320/1
Figure 1.7. Digital Crossbar Diagram
1.7. Serial Ports
The C8051F320/1 Family includes an SMBus/I
2
C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programma-
ble capture/compare modules. The PCA clock is derived fr
om one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8. The external clock source selection is useful for real-time
clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the
system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Sof
tware Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1
2
6
PCA
CP1
Outputs
2
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
P2
I/O
Cells
P2.0
P2.7
8
P3
I/O
Cells
P3.0
1
(Port Latches)
P0
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
8
8
8
8
P1
P2
P3
Note: P2.4-P2.7 only available
on the C8051F320
