Rev. 1.4 19

C8051F320/1

Figure 1.3. On-Chip Clock and Reset

1.2. On-Chip Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data

RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general

purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of

RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of

general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.

Program memory consists of 16 kB of Flash. This me

mory may be reprogrammed in-system in 512 byte

sectors, and requires no special off-chip programming voltage. See Figure 1.4 for the MCU system mem-

ory map.

PCA

WDT

Missing

Clock

Detector

(one-

shot)

Software Reset (SWRSF)

System Reset

Reset

Funnel

Px.x

System

Clock

CIP-51

Microcontroller

Core

Extended Interrupt

Handler

Clock Select

WDT

Enable

MCD

Enable

Errant

FLASH

Operation

Comparator 0

C0RSEF

/RST

(wired-OR)

Power On

Reset

VDD

Supply

Monitor

Enable

'0'

Internal

Oscillator

XTAL1

XTAL2

External

Oscillator

Drive

Clock

Multiplier

USB

Controller

VBUS

Transition

Enable

C8051F320/1

20 Rev. 1.4

Figure 1.4. On-Board Memory Map

1.3. Universal Serial Bus Controller

The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with inte-

grated transceiver and endpoint FIFO RAM. A total of e

ight endpoint pipes are available: a bi-directional

control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).

A 1k block of XRAM is used as dedicated USB FIFO sp

ace. This FIFO space is distributed among

Endpoints0–3; Endpoint1–3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode).

The maximum FIFO size is 512 bytes (Endpoint3).

USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery cir-

cuitry allow both Full and Low Speed options to

be implemented with the on-chip precision oscillator as the

USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate

the USB clock. The CPU clock source is independent of the USB clock.

Same 2048 bytes as from

0x0000 to 0x07FF, wrapped

on 2 kB boundaries

PROGRAM/DATA MEMORY

(Flash)

(Direct and Indirect

Addressing)

0x00

0x7F

Upper 128 RAM

(Indirect Addressing

Only)

0x80

0xFF

Special Function

(Direct Addressing Only)

DATA MEMORY (RAM)

General Purpose

Registers

0x1F

0x20

0x2F

Bit Addressable

Lower 128 RAM

(Direct and Indirect

Addressing)

0x30

INTERNAL DATA ADDRESS SPACE

EXTERNAL DATA ADDRESS SPACE

XRAM - 1024 Bytes

(accessable using MOVX

instruction)

0x0000

0x03FF

0x0400

0xFFFF

16 K Flash

(In-System

Programmable in 512

Byte Sectors)

0x0000

RESERVED

0x3E00

0x3DFF

0x07FF

0x0800

USB FIFOs

1024 Bytes

Rev. 1.4 21

C8051F320/1

The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull-

up resistors can be enabled/disabled in software, and will appear on the D+ or D– pin according to the soft

ware-selected speed setting (Full or Low Speed).

Figure 1.5. USB Controller Block Diagram

1.4. Voltage Regulator

C8051F320/1 devices include a 5-to-3 V voltage regulator (REG0). When enabled, the REG0 output

appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by

software.

1.5. On-Chip Debug Circuitry

The C8051F320/1 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intru-

sive, full speed, in-circuit debugging of the production part inst

alled in the end application.

Silicon Labs' debugging system support

s inspection and modification of memory and registers, break-

points, and single stepping. No additional target RAM, pr

ogram memory, timers, or communications chan-

nels are required. All the digital and analog peripherals

are functional and work correctly while debugging.

All the peripherals (except for the USB, ADC, and SMBus) are stalled when the MCU is halted, during sin-

gle stepping, or at a breakpoint in order to keep them synchronized.

The C8051F320DK development kit provides all the hardwar

e and software necessary to develop applica-

tion code and perform in-circuit debugging with the C8

051F320/1 MCUs. The kit includes software with a

developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a debug

adapter. It also has a target application board with the C8051F320 MCU installed, the necessary cables for

connection to a PC, and a wall-mount power supply. The development kit contents may also be used to

program and debug the device on the production PCB using the appropriate connections for the program-

ming pins.

The Silicon Labs IDE interface is a vastl

y superior developing and debugging configuration, compared to

standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to

Transceiver Serial Interface Engine (SIE)

USB FIFOs

(1k RAM)

D+

D-

VDD

Endpoint0

IN/OUT

Endpoint1

IN OUT

Endpoint2

IN OUT

Endpoint3

IN OUT

Data

Transfer

Control

CIP-51 Core

USB

Control,

Status, and

Interrupt

Registers

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

Related Items

Technical Document