Rev. 1.4 151

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USB Register Definition 15.8. POWER: USB0 Power

Bit7: ISOUD: ISO Update

This bit affects all IN Isochronous endpoints.

0: When software writes INPRDY = ‘1’, USB0 will send the packet when the next IN token is

received.

1: When software writes INPRDY = ‘1’, USB0 will wait for a SOF token before sending the

packet. If an IN token is received before a SOF token, USB0 will send a zero-length data

packet.

Bits6–5: Unused. Read = 00b. Write = don’t care.

Bit4: USBINH: USB0 Inhibit

This bit is set to ‘1’ following a power-on reset (POR) or an asynchronous USB0 reset (see

Bit3: RESET). Software should clear this bit after all USB0 and transceiver initialization is

complete. Software cannot set this bit to ‘1’.

0: USB0 enabled.

1: USB0 inhibited. All USB traffic is ignored.

Bit3: USBRST: Reset Detect

Writing ‘1’ to this bit forces an asynchronous USB0 reset. Reading this bit provides bus reset

status information.

Read:

0: Reset signaling is not present on the bus.

1: Reset signaling detected on the bus.

Bit2: RESUME: Force Resume

Software can force resume signaling on the bus to wake USB0 from suspend mode. Writing

a ‘1’ to this bit while in Suspend mode (SUSMD = ‘1’) forces USB0 to generate Resume sig-

naling on the bus (a remote Wakeup event). Software should write RESUME = ‘0’ after

10 ms to15 ms to end the Resume signaling. An interrupt is generated, and hardware clears

SUSMD, when software writes RESUME = ‘0’.

Bit1: SUSMD: Suspend Mode

Set to ‘1’ by hardware when USB0 enters suspend mode. Cleared by hardware when soft-

ware writes RESUME = ‘0’ (following a remote wakeup) or reads the CMINT register after

detection of Resume signaling on the bus.

0: USB0 not in suspend mode.

1: USB0 in suspend mode.

Bit0: SUSEN: Suspend Detection Enable

0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.

1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling

on the bus.

R/W R/W R/W R/W R/W R/W R R/W Reset Value

ISOUD - - USBINH USBRST RESUME SUSMD SUSEN 00010000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:

0x01

C8051F320/1

152 Rev. 1.4

USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low

USB Register Definition 15.10. FRAMEH: USB0 Frame Number High

15.8. Interrupts

The read-only USB0 interrupt flags are located in the USB registers shown in Figure 15.11 through

Figure 15.13. The associated interrupt enable bits are located in the USB registers shown in Figure 15.14

through Figure 15.16. A USB0 interrupt is generated when any of the U

SB interrupt flags is set to ‘1’. The

USB0 interrupt is enabled via the EIE1 SFR (see Section “9.3. Interrupt Handler” on page 87).

Note: Reading a USB interrupt flag register resets all flags in that register to ‘0’.

Bits7-0: Frame Number Low

This register contains bits7-0 of the last received frame number.

RRRRRRRRReset Value

Frame Number Low 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:

0x0C

Bits7-3: Unused. Read = 0. Write = don’t care.

Bits2-0: Frame Number High Byte

This register contains bits10-8 of the last received frame number.

RRRRRRRRReset Value

- - - - - Frame Number High 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:

0x0D

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C8051F320/1

USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt

Bits7–4: Unused. Read = 0000b. Write = don’t care.

Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag

This bit is cleared when software reads the IN1INT register.

0: IN Endpoint 3 interrupt inactive.

1: IN Endpoint 3 interrupt active.

Bit2: IN2: IN Endpoint 2 Interrupt-pending Flag

This bit is cleared when software reads the IN1INT register.

0: IN Endpoint 2 interrupt inactive.

1: IN Endpoint 2 interrupt active.

Bit1: IN1: IN Endpoint 1 Interrupt-pending Flag

This bit is cleared when software reads the IN1INT register.

0: IN Endpoint 1 interrupt inactive.

1: IN Endpoint 1 interrupt active.

Bit0: EP0: Endpoint 0 Interrupt-pending Flag

This bit is cleared when software reads the IN1INT register.

0: Endpoint 0 interrupt inactive.

1: Endpoint 0 interrupt active.

RRRRRRRRReset Value

- - - - IN3 IN2 IN1 EP0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:

0x02

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document