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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Rev. 1.4 145
C8051F320/1
USB Register Definition 15.4. INDEX: USB0 Endpoint Index
Indexed Registers
E0CSR
0x11
Endpoint0 Control / Status 160
EINCSRL Endpoint IN Control / Status Low Byte 163
EINCSRH 0x12 Endpoint IN Control / Status High Byte 164
EOUTCSRL 0x14 Endpoint OUT Control / Status Low Byte 166
EOUTCSRH 0x15 Endpoint OUT Control / Status High Byte 167
E0CNT
0x16
Number of Received Bytes in Endpoint0 FIFO 161
EOUTCNTL Endpoint OUT Packet Count Low Byte 167
EOUTCNTH 0x17 Endpoint OUT Packet Count High Byte 167
Table 15.2. USB0 Controller Registers (Continued)
USB Register
Name
USB Register
Address
Description Page Number
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bits3–0: EPSEL: Endpoint Select
These bits select which endpoint is targeted when indexed USB0 registers are accessed.
R R R R R/W R/W R/W R/W Reset Value
- - - - EPSEL 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:
0x0E
INDEX Target Endpoint
0x0 0
0x1 1
0x2 2
0x3 3
0x4–0xF Reserved
C8051F320/1
146 Rev. 1.4
15.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed fu
nction, the USB0 clock must be 48 MHz. Clock options
are described in Section “13. Oscillators” on page 116. The USB0 clock is selected
via SFR CLKSEL (see
Figure 13.5 on Page 124).
Clock Recovery circuitry uses the incoming USB
data stream to adjust the internal oscillator; this allows
the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock
Recovery should be used in the following configurations:
When operating USB0 as a Low Speed function with
Clock Recovery, software must write ‘1’ to the
CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed
mode.
Single Step Mode can be used to help the Clock Recove
ry circuitry to lock when high noise levels are pres-
ent on the USB network. This mode is not require
d (or recommended) in typical USB environments.
USB Register Definition 15.5. CLKREC: Clock Recovery Control
Communication Speed USB Clock 4x Clock Multiplier Input
Full Speed 4x Clock Multiplier Internal Oscillator
Low Speed Internal Oscillator/2 N/A
Bit7: CRE: Clock Recovery Enable.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
Bit6: CRSSEN: Clock Recovery Single Step.
This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery.
0: Normal calibration mode.
1: Single step mode.
Bit5: CRLOW: Low Speed Clock Recovery Mode.
This bit must be set to ‘1’ if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
Bits4–0: Reserved. Read = Variable. Must Write = 1001b.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
CRE CRSSEN CRLOW Reserved 00001001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address:
0x0F
Rev. 1.4 147
C8051F320/1
15.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between
Endpoints0-3 as shown in Figure 15.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT,
or both (Split Mode: half IN, half OUT).
Figure 15.3. USB FIFO Allocation
15.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that
endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see Figure 15.20).
Endpoint0
(64 bytes)
Configurable as
IN, OUT, or both (Split
Mode)
Free
(64 bytes)
0x0400
0x043F
0x0440
0x063F
0x0640
0x073F
0x0740
0x07BF
0x07C0
0x07FF
User XRAM
(1024 bytes)
0x0000
0x03FF
USB Clock Domain
System Clock Domain
Endpoint1
(128 bytes)
Endpoint2
(256 bytes)
Endpoint3
(512 bytes)
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