C8051F320/1
136 Rev. 1.4
SFR Definition 14.12. P2MDIN: Port2 Input Mode Register
SFR Definition 14.13. P2MDOUT: Port2 Output Mode Register
SFR Definition 14.14. P2SKIP: Port2 Skip Register
Bits7–0: Analog Input Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P2.n pin is configured as an analog input.
1: Corresponding P2.n pin is not configured as an analog input.
Note: P2.7–P2.4 only available on C8051F320 devices.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xF3
Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis-
ter P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: P2.7–P2.4 only available on C8051F320 devices.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xA6
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bits3–0: P2SKIP[3:0]: Port2 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xD6
