C8051F320/1
126 Rev. 1.4
14. Port Input/Output
Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321).
Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose
I/O (GPIO) or analog input; Port pins
P0.0-P2.3 can be assigned to one of the internal digital resources as
shown in Figure 14.3. The designer has complete control over which functions ar
e assigned, limited only
by the number of physical I/O pins. This resource assi
gnment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resou
r
ces to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.1 and Figure 14.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output M
ode
registers (PnMDOUT, where n = 0,1,2,3). Com-
plete Electrical Specifications for Port
I/O are given in Table 14.1 on page 138.
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1
2
6
PCA
CP1
Outputs
2
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
P2
I/O
Cells
P2.0
P2.7
8
P3
I/O
Cells
P3.0
1
(Port Latches)
P0
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
8
8
8
8
P1
P2
P3
Note: P2.4-P2.7 only available
on the C8051F320
Figure 14.1. Port I/O Functional Block Diagram
