Rev. 1.4 13

C8051F320/1

SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 131

SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 132

SFR Definition 14.3. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SFR Definition 14.4. P0MDIN: Port0 Input Mode Register . . . . . . . . . . . . . . . . . . . . . 133

SFR Definition 14.5. P0MDOUT: Port0 Output Mode Register . . . . . . . . . . . . . . . . . 133

SFR Definition 14.6. P0SKIP: Port0 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

SFR Definition 14.7. P1: Port1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

SFR Definition 14.8. P1MDIN: Port1 Input Mode Register . . . . . . . . . . . . . . . . . . . . . 134

SFR Definition 14.9. P1MDOUT: Port1 Output Mode Register . . . . . . . . . . . . . . . . . 135

SFR Definition 14.10. P1SKIP: Port1 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SFR Definition 14.11. P2: Port2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SFR Definition 14.12. P2MDIN: Port2 Input Mode Register . . . . . . . . . . . . . . . . . . . . 136

SFR Definition 14.13. P2MDOUT: Port2 Output Mode Register . . . . . . . . . . . . . . . . 136

SFR Definition 14.14. P2SKIP: Port2 Skip Register . . . . . . . . . . . . . . . . . . . . . . . . . . 136

SFR Definition 14.15. P3: Port3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SFR Definition 14.16. P3MDIN: Port3 Input Mode Register . . . . . . . . . . . . . . . . . . . . 137

SFR Definition 14.17. P3MDOUT: Port3 Output Mode Register . . . . . . . . . . . . . . . . 137

SFR Definition 15.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 141

SFR Definition 15.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 143

SFR Definition 15.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

USB Register Definition 15.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 145

USB Register Definition 15.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 146

USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 148

USB Register Definition 15.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 149

USB Register Definition 15.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 151

USB Register Definition 15.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 152

USB Register Definition 15.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 152

USB Register Definition 15.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . 153

USB Register Definition 15.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 154

USB Register Definition 15.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 155

USB Register Definition 15.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 156

USB Register Definition 15.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 156

USB Register Definition 15.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 157

USB Register Definition 15.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 160

USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 161

USB Register Definition 15.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 163

USB Register Definition 15.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 164

USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte . .

166

USB Register Definition 15.22. EOUTCSRH: USB0 OUT Endpoint Control Low Byte . .

167

USB Register Definition 15.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 167

USB Register Definition 15.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 167

SFR Definition 16.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 175

SFR Definition 16.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

C8051F320/1

14 Rev. 1.4

SFR Definition 16.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

SFR Definition 17.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 192

SFR Definition 17.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 193

SFR Definition 18.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 203

SFR Definition 18.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

SFR Definition 18.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

SFR Definition 18.4. SPI0DAT: SPI0 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 205

SFR Definition 19.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

SFR Definition 19.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

SFR Definition 19.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

SFR Definition 19.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

SFR Definition 19.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

SFR Definition 19.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

SFR Definition 19.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

SFR Definition 19.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

SFR Definition 19.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 221

SFR Definition 19.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 221

SFR Definition 19.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

SFR Definition 19.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

SFR Definition 19.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

SFR Definition 19.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 226

SFR Definition 19.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 226

SFR Definition 19.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

SFR Definition 19.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

SFR Definition 20.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

SFR Definition 20.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

SFR Definition 20.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 242

SFR Definition 20.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 243

SFR Definition 20.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 243

SFR Definition 20.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 243

SFR Definition 20.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 244

C2 Register Definition 21.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

C2 Register Definition 21.2. C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

C2 Register Definition 21.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 246

C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 246

C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 246

Rev. 1.4 15

C8051F320/1

1. System Overview

C8051F320/1 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are

listed below. Refer to Table 1.1 for specific product feature selection.

• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)

• In-system, full-speed, non-intrusive debug interface (on-chip)

• Universal Serial Bus (USB) Function Controller with eigh

t flexible endpoint pipes, integrated trans-

ceiver, and 1k FIFO RAM

• Supply Voltage Regulator (5-to-3 V)

• True 10-bit 200 ksps 17-channel single-ended/differential AD

C with analog multiplexer

• On-chip Voltage Reference and Temperature Sensor

• On-chip Voltage Comparators (2)

• Precision programmable 12 MHz internal oscillator and 4x clock multiplier

• 16 kB of on-chip Flash memory

• 2304 total bytes of on-chip RAM (256 + 1k + 1k USB FIFO)

•SMBus/I

C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware

• Four general-purpose 16-bit timers

• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer

func

tion

• On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector

• 25/21 Port I/O (5 V tolerant)

With on-chip Power-On Reset, VDD

monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,

C8051F320/1 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be repro-

grammed in-circuit, providing no

n-volatile data storage, and also allowing field upgrades of the 8051 firm-

ware. User software has complete control of all peripherals and may individually sh

ut down any or all

peripherals for power savings.

The on-chip Silicon Labs 2-Wire (C2) D

evelopment Interface allows non-intrusive (uses no on-chip

resources), full speed, in-circuit debugging using the production MCU installed in the final application. This

debug logic supports inspection and modification of memory and registers, setting breakpoints, single

stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging

using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-

out occupying package pins.

Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–40 to +85 °C).

(

Note that 3.0-to-3.6 V is required for USB communication.) The Po

rt I/O and /RST pins are tolerant of

input signals up to 5 V. C8051F320/1 are available in a 32-pin LQFP or a 28-pin QFN package.

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document