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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
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SILICON LABS
Date Code: 0603
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F320/1
118 Rev. 1.4
Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0,
then the device will not be capable of producing the desired frequency.
13.1.2. Internal Oscillator Suspend Mode
The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register
OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Sec-
tion 15) or VBUS matches the polarity selected by the
VBPOL bit in register REG0CN (Section 8.2). The
transceiver is able to detect non-idle USB events even
when it is placed in Suspend mode. On a non-idle
USB event, a Resume interrupt is generated, on receipt of which the PHYEN bit should be set to '1' to re-
enable the transceiver.
SFR Definition 13.1. OSCICN: Internal Oscillator Control
SFR Definition 13.2. OSCICL: Internal Oscillator Calibration
Bit7: IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
Bit6: IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
Bit5: SUSPEND: Force Suspend
Writing a ‘1’ to this bit will force the internal oscillator to be stopped. The oscillator will be re-
started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event
(see Figure 8.1).
Bits4–2: UNUSED. Read = 000b, Write = don't care.
Bits1–0: IFCN1–0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
R/W R R/W R R/W R/W R/W R/W Reset Value
IOSCEN IFRDY SUSPEND - - - IFCN1 IFCN0 10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB2
Bits7–5: Unused: Read = varies. Write = don’t care.
Bits4–0: OSCCAL: Oscillator Calibration Value
These bits determine the internal oscillator period as per Equation 13.1.
Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “15.4. USB Clock
Configuration” on page 146 for details on Clock Recovery.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
--- OSCCAL Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB3
Rev. 1.4 119
C8051F320/1
13.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1
and XTAL2 pins as shown in Option 1 of Figure 13.1. A
10 Mr
esistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS clo
ck configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 13.1. The type of external oscillator must
be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see Figure 13.3)
Important Note on External Oscillator Usage: Po
rt pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “14.1. Priority Crossbar
Decoder” on page 128 for Crossbar configuration. Additionally
, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as ana
log inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “14.2. Port
I/O Initialization” on page 130 for details on Port input mode s
election.
13.2.1. Clocking Timers Directly Through the External Oscillator
The external oscillator source divided by eight is a clock option for the timers (Section “19. Timers” on
page 209) and the Programmable Counter Array (PCA) (Section “20. Programmable Counter Array
(PCA0)” on page 227). When the external oscillator
is used to clock these peripherals, but is not used as
the system clock, the external oscillator frequency must be less than or equal
to the system clock fre-
quency. In this configuration, the clock supplied to the peripheral (external oscillator
/ 8) is synchronized
with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles.
13.2.2. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency
Control value (XFCN)
should be chosen from the Crystal column of the table in Figure 13.3 (OSCXCN register).
For example, a
12 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the oscillator
amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and c
hecking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The rec-
ommended procedure is:
Step 1. Enable the external oscillator.
S
tep 2. Wait at least 1 ms.
Step 3. Poll for XTLVLD => ‘1’.
Step 4. Switch the system clock to the external oscillator.
Important Note on External Crystals:
Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
C8051F320/1
120 Rev. 1.4
13.2.3. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency
Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100 kHz, let R = 246 k an
d C = 50 pF:
f = 1.23( 10
3
) / RC = 1.23 ( 10
3
) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in Figure 13.3, the required XFCN setting is 010b. Programming XFCN to a higher
setting in RC mode will improve frequency acc
uracy at an increased external oscillator supply current.
13.2.4. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 13.1, Option 3. The capacitor should be no greater than 100 pF; however for very small
capacitors,
the total capacitance may be dominated by parasitic ca
pacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the
frequency of oscillation from the equations below. Assume VDD = 3.0 V and C
= 50 pF:
f = KF / ( C x VDD ) = KF / ( 50 x 3 ) MHz
f = KF / 150 MHz
If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 13.3 as KF = 22:
f = 22 / 150 = 0.146 MHz, or 146 kHz
Therefore, the XFCN value to use in this example is 011b.
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