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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
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276 + $6.46859
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SILICON LABS
Date Code: 0603
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Endpoint0
(64 bytes)
Free
(64 bytes)
0x0400
0x043F
0x0440
0x063F
0x0640
0x073F
0x0740
0x07BF
0x07C0
0x07FF
User XRAM
(1024 bytes)
0x0000
0x03FF
Endpoint1
(128 bytes)
Endpoint2
(256 bytes)
Endpoint3
(512 bytes)
USB FIFO Space
(USB Clock Domain)
User XRAM Space
(System Clock Domain)
SFR Definition 12.1.
Bits7–3: Unused: Read = 00000b. Write = don’t care.
Bits2–0: PGSEL[2:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM. The upper 5-bits are "don't cares", so the 2k address blocks are repeated modulo over
the entire 64k external data memory address space.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - PGSEL2 PGSEL1 PGSEL0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xAA
EMI0CN: External Memory Interface Control
Rev. 1.4 115
C8051F320/1
Figure 12.2. XRAM Memory Map Expanded View
C8051F320/1
116 Rev. 1.4
13. Oscillators
C8051F320/1 devices include a programmable internal oscillator, an external oscillator drive circuit, and a
4x Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and
OSCICL registers, as shown in Figure 13.1. The system clock (SYSCLK) can be derived from the internal
oscillator, external oscillator circuit, or
the
4x Clock Multiplier divided by 2. The USB clock (USBCLK) can
be derived from the internal oscillator, external oscillator, or 4x Clock Multiplier. Oscillator electrical specifi-
cations are given in Table 13.3 on page 125.
Clock Multiplier
OSC
EXOSC
Input
Circuit
XTLVLD
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10M
Option 3
XTAL2
Option 4
XTAL2
OSCXCN
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
CLKMUL
MULEN
MULINIT
MULRDY
MULSEL1
MULSEL0
Programmable
Internal Clock
Generator
EN
OSCICL OSCICN
IOSCEN
IFRDY
SUSPEND
IFCN1
IFCN0
IOSC
n
EXOSC / 2
x 2 x 2EXOSC
IOSC
SYSCLK
EXOSC
EXOSC / 2
EXOSC / 3
EXOSC / 4
IOSC / 2
USBCLK
USBCLK2-0
CLKSEL
USBCLK2
USBCLK1
USBCLK0
CLKSL1
CLKSL0
Figure 13.1. Oscillator Diagram
13.1. Programmable Internal Oscillator
All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after
a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by
Equation 13.1, where f
BASE
is the frequency of the internal oscillator following a reset, T is the change in
internal oscillator period, and OSCICL is a c
hange to the value held in register OSCICL.
Equation 13.1. Typical Change in Internal Oscillator Period with OSCICL
T 0.0025
1
f
BASE
-------------
OSCICL
On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (f
BASE
). Sec-
tion 13.1.1 details oscillator programming for C8051F320/1 devices. Electrical
specifications for the preci-
sion internal oscillator are given in Table 13.3 on page 125. Note that the system clock may be derived
from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN
bits in register
OSCICN. The divide value defaults to 8 following a reset.
The OSCICL reset value is factory calibrated to result in a 12 MHz internal os
cillator with a ±1.5% accu-
racy; this frequency is suitable for us
e as the USB clock (see Section 13.4). Software may modify the fre-
quency of the internal oscillator as described below.
Important Note: Once
the internal oscillator frequency has been modified, the internal oscillator may not
be used as the USB clock as described in Section 13.4. The internal oscillator frequency will reset to it
s
original factory-calibrated frequency following any device
reset, at which point the oscillator is suitable for
use as the USB clock.
Software should read and adjust the value of OSCICL according to Equation 13.1 to obtain the desired fre-
quency. The example below shows how to obtain an 11.6 MHz internal oscillator frequency.
f
BASE
is the internal oscillator reset frequency; T
BASE
is the reset oscillator period.
f
DES
is the desired internal oscillator frequency; T
DES
is the desired oscillator period.
The required change in period (T
DES
) is the difference between the base period and the desired period.
Using Equation 13.1 and the above calculations, find OSCICL:
OSCICL is rounded to the nearest integer (14) and added to the reset value of register OSCICL.
f
BASE
12000000Hz=
T
BASE
1
12000000
------------------------
s=
f
DES
11600000Hz=
T
DES
1
11600000
------------------------
s=
T
DES
1
11600000
------------------------
1
12000000
------------------------
2.87 10
9
s==
2.87 10
9
0.0025
1
f
BASE
-------------
OSCICL=
OSCICL 13.79=
Rev. 1.4 117
C8051F320/1
13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices
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