C8051F320/1

112 Rev. 1.4

SFR Definition 11.1.

Bits7–3: Unused: Read = 00000b. Write = don’t care.

Bit2: Reserved. Read = 0b. Must Write = 0b.

Bit1: PSEE: Program Store Erase Enable

Setting this bit (in combination with PSWE) allows an entire page of Flash program memory

to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to

Flash memory using the MOVX instruction will erase the entire page that contains the loca-

tion addressed by the MOVX instruction. The value of the data byte written does not matter.

0: Flash program memory erasure disabled.

1: Flash program memory erasure enabled.

Bit0: PSWE: Program Store Write Enable

Setting this bit allows writing a byte of data to the Flash program memory using the MOVX

write instruction. The Flash location should be erased before writing data.

0: Writes to Flash program memory disabled.

1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash

memory.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - - - - Reserved PSEE PSWE 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0x8F

PSCTL: Program Store R/W Control

SFR Definition 11.2.

Bits7–0: FLKEY: Flash Lock and Key Register

Write:

This register must be written to before Flash writes or erases can be performed. Flash

remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The

timing of the writes does not matter, as long as the codes are written in order. The key codes

must be written for each Flash write or erase operation. Flash will be locked until the next

system reset if the wrong codes are written or if a Flash operation is attempted before the

codes have been written correctly.

Read:

When read, bits 1–0 indicate the current Flash lock state.

00: Flash is write/erase locked.

01: The first key code has been written (0xA5).

10: Flash is unlocked (writes/erases allowed).

11: Flash writes/erases disabled until the next reset.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xB7

FLKEY: Flash Lock and Key

Rev. 1.4 113

C8051F320/1

SFR Definition 11.3.

Bits7: FOSE: Flash One-shot Enable

This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash

sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen-

cies below 10 MHz, disabling the Flash one-shot will increase system power consumption.

0: Flash one-shot disabled.

1: Flash one-shot enabled.

Bits6–0: RESERVED. Read = 000000b. Must Write 000000b.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xB6

FLSCL: Flash Scale

C8051F320/1

114 Rev. 1.4

12. External RAM

The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM

(addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF).

XRAM

1024 Bytes

0x0000

0x03FF

Same 2048 bytes as from

0x0000 to 0x07FF, wrapped

on 2 kB boundaries

0x0400

0xFFFF

USB FIFOs

1024 Bytes

0x07FF

0x0800

Accessed through USB FIFO

registers

Accessed with the MOVX

instruction

Figure 12.1. External Ram Memory Map

12.1. Accessing User XRAM

XRAM can be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using

MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as

@R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Reg-

ister (EMI0CN as shown in Figure 12.1). Note: the MOVX instruction is also used for writes to the Flash

memory. See Section “11. Flash Memory” on page 106 for details. The MOVX inst

ruction accesses XRAM

y default.

For any of the addressing modes the upper 5 bits of the

16-bit external data memory address word are

"don't cares". As a result, the 2048-byte RAM is mapped modulo style over the entire 64k external data

memory address range. For example, the XRAM byte at address 0x0000 is also at address 0x0800,

0x1000, 0x1800, 0x2000, etc.

Important Note: The upper 1k of the 2k XRAM functions as USB FIFO space. See Section 12.2 for

details on accessing this memory space.

12.2. Accessing USB FIFO Space

The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO

space and user XRAM. FIFO space is acce

ssed via USB FIFO registers; see Section “15.5. FIFO Manage-

ment” on page 147 for more information on accessing these FIFOs. The MOVX instru

ction should not be

used to load or modify USB data in the FIFO space.

Unused areas of the FIFO space may be used as gener

al pu

rpose XRAM, accessible as described in Sec-

tion 12.1. The FIFO block operates on the USB clock domain; th

us the USB clock must be active when

accessing FIFO space. Note that the number of SYSCLK cycles required by the MOVX

instruction is

increased when accessing USB FIFO space.

Important Note: The USB clock must be

tive when accessing FIFO space.

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document