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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
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SILICON LABS
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Rev. 1.4 103
C8051F320/1
10.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of th
e /RST pin is unaffected by this reset.
10.9. USB Reset
Writing ‘1’ to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB
network. The USB Function Controller (USB0) must
be enabled for RESET signaling to be detected. See Section “15. Universal Serial Bus Con-
troller (USB)” on page 139 for information on the USB Function Controller.
2. The voltage on the VBUS pin matches the polarity selected by the VBPOL bit
in register
REG0CN. See Section “8. Voltage Regulator (REG0)” on page 67 for details on the VBUS
detection circuit.
The USBRSF bit will read ‘1’ following a USB reset. The st
ate of the /RST pin is unaffected by this reset.
C8051F320/1
104 Rev. 1.4
SFR Definition 10.2.
Bit7: USBRSF: USB Reset Flag
0: Read: Last reset was not a USB reset; Write: USB resets disabled.
1: Read: Last reset was a USB reset; Write: USB resets enabled.
Bit6: FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
Bit5: C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0; Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0; Write: Comparator0 is a reset source
(active-low).
Bit4: SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit; Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit; Write: Forces a system reset.
Bit3: WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
Bit2: MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout; Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout; Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
Bit1: PORSF: Power-On / VDD Monitor Reset Flag.
This bit is set anytime a power-on reset occurs. Writing this bit selects/deselects the VDD
monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
and stabilized can cause a system reset. See register VDM0CN (Figure 10.1).
0: Read: Last reset was not a power-on or VDD monitor reset; Write: VDD monitor is not a
reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indetermi-
nate; Write: VDD monitor is a reset source.
Bit0: PINRSF: HW Pin Reset Flag.
0: Source of last reset was not /RST pin.
1: Source of last reset was /RST pin.
Note: For bits that act as both reset source enables (on a write) and reset indicator flags (on a
read), read-modify-write instructions read and modify the source enable only. This applies to
bits: USBRSF, C0RSEF, SWRSF, MCDRSF, PORSF.
R/W R R/W R/W R R/W R/W R Reset Value
USBRSF FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xEF
RSTSRC: Reset Source
Table 10.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
Rev. 1.4 105
C8051F320/1
Parameter Conditions Min Typ Max Units
/RST Output Low Voltage
I
OL
= 8.5 mA, VDD = 2.7 V to 3.6 V
0.6 V
/RST Input High Voltage 0.7 x VDD V
/RST Input Low Voltage 0.3 x VDD
/RST Input Pull-Up Current /RST = 0.0 V 25 40 µA
VDD POR Threshold (V
RST
)
2.40 2.55 2.70 V
Missing Clock Detector Timeout
Time from last system clock rising
edge to reset initiation
100 220 500 µs
Reset Time Delay
Delay between release of any
reset source and code execution
at location 0x0000
5.0 µs
Minimum /RST Low Time to
Generate a System Reset
15 µs
VDD Monitor Turn-on Time 100 µs
VDD Monitor Supply Current 20 50 µA
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