Rev. 1.4 91

C8051F320/1

SFR Definition 9.7.

Bit7: EA: Enable All Interrupts.

This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-

tings.

0: Disable all interrupt sources.

1: Enable each interrupt according to its individual mask setting.

Bit6: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.

This bit sets the masking of the SPI0 interrupts.

0: Disable all SPI0 interrupts.

1: Enable interrupt requests generated by SPI0.

Bit5: ET2: Enable Timer 2 Interrupt.

This bit sets the masking of the Timer 2 interrupt.

0: Disable Timer 2 interrupt.

1: Enable interrupt requests generated by the TF2L or TF2H flags.

Bit4: ES0: Enable UART0 Interrupt.

This bit sets the masking of the UART0 interrupt.

0: Disable UART0 interrupt.

1: Enable UART0 interrupt.

Bit3: ET1: Enable Timer 1 Interrupt.

This bit sets the masking of the Timer 1 interrupt.

0: Disable all Timer 1 interrupt.

1: Enable interrupt requests generated by the TF1 flag.

Bit2: EX1: Enable External Interrupt 1.

This bit sets the masking of External Interrupt 1.

0: Disable external interrupt 1.

1: Enable interrupt requests generated by the /INT1 input.

Bit1: ET0: Enable Timer 0 Interrupt.

This bit sets the masking of the Timer 0 interrupt.

0: Disable all Timer 0 interrupt.

1: Enable interrupt requests generated by the TF0 flag.

Bit0: EX0: Enable External Interrupt 0.

This bit sets the masking of External Interrupt 0.

0: Disable external interrupt 0.

1: Enable interrupt requests generated by the /INT0 input.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable)

0xA8

IE: Interrupt Enable

C8051F320/1

92 Rev. 1.4

SFR Definition 9.8.

Bit7: UNUSED. Read = 1b, Write = don't care.

Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.

This bit sets the priority of the SPI0 interrupt.

0: SPI0 interrupt set to low priority level.

1: SPI0 interrupt set to high priority level.

Bit5: PT2: Timer 2 Interrupt Priority Control.

This bit sets the priority of the Timer 2 interrupt.

0: Timer 2 interrupt set to low priority level.

1: Timer 2 interrupts set to high priority level.

Bit4: PS0: UART0 Interrupt Priority Control.

This bit sets the priority of the UART0 interrupt.

0: UART0 interrupt set to low priority level.

1: UART0 interrupts set to high priority level.

Bit3: PT1: Timer 1 Interrupt Priority Control.

This bit sets the priority of the Timer 1 interrupt.

0: Timer 1 interrupt set to low priority level.

1: Timer 1 interrupts set to high priority level.

Bit2: PX1: External Interrupt 1 Priority Control.

This bit sets the priority of the External Interrupt 1 interrupt.

0: External Interrupt 1 set to low priority level.

1: External Interrupt 1 set to high priority level.

Bit1: PT0: Timer 0 Interrupt Priority Control.

This bit sets the priority of the Timer 0 interrupt.

0: Timer 0 interrupt set to low priority level.

1: Timer 0 interrupt set to high priority level.

Bit0: PX0: External Interrupt 0 Priority Control.

This bit sets the priority of the External Interrupt 0 interrupt.

0: External Interrupt 0 set to low priority level.

1: External Interrupt 0 set to high priority level.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable)

0xB8

IP: Interrupt Priority

Rev. 1.4 93

C8051F320/1

SFR Definition 9.9.

Bit7: ET3: Enable Timer 3 Interrupt.

This bit sets the masking of the Timer 3 interrupt.

0: Disable Timer 3 interrupts.

1: Enable interrupt requests generated by the TF3L or TF3H flags.

Bit6: ECP1: Enable Comparator1 (CP1) Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 interrupts.

1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.

Bit5: ECP0: Enable Comparator0 (CP0) Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 interrupts.

1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.

Bit4: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.

This bit sets the masking of the PCA0 interrupts.

0: Disable all PCA0 interrupts.

1: Enable interrupt requests generated by PCA0.

Bit3: EADC0: Enable ADC0 Conversion Complete Interrupt.

This bit sets the masking of the ADC0 Conversion Complete interrupt.

0: Disable ADC0 Conversion Complete interrupt.

1: Enable interrupt requests generated by the AD0INT flag.

Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 Window Comparison interrupt.

0: Disable ADC0 Window Comparison interrupt.

1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).

Bit1: EUSB0: Enable USB0 Interrupt.

This bit sets the masking of the USB0 interrupt.

0: Disable all USB0 interrupts.

1: Enable interrupt requests generated by USB0.

Bit0: ESMB0: Enable SMBus (SMB0) Interrupt.

This bit sets the masking of the SMB0 interrupt.

0: Disable all SMB0 interrupts.

1: Enable interrupt requests generated by SMB0.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xE6

EIE1: Extended Interrupt Enable 1

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document