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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
Availability In Stock
Qty 560
Qty Price
1 - 24 $10.41286
25 - 60 $8.28296
61 - 128 $7.80964
129 - 275 $7.25745
276 + $6.46859
Manufacturer Available Qty
SILICON LABS
Date Code: 0603
  • Shipping Freelance Stock: 560
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F320/1
10 Rev. 1.4
Figure 16.2. Typical SMBus Configuration............................................................. 170
Figure 16.3. SMBus Transaction............................................................................ 171
Table 16.1. SMBus Clock Source Selection........................................................... 173
Figure 16.4. Typical SMBus SCL Generation......................................................... 174
Table 16.2. Minimum SDA Setup and Hold Times................................................. 174
Table 16.3. Sources for Hardware Changes to SMB0CN ...................................... 178
Figure 16.5. Typical Master Transmitter Sequence................................................ 180
Figure 16.6. Typical Master Receiver Sequence.................................................... 181
Figure 16.7. Typical Slave Receiver Sequence...................................................... 182
Figure 16.8. Typical Slave Transmitter Sequence.................................................. 183
Table 16.4. SMBus Status Decoding...................................................................... 184
17.UART0
Figure 17.1. UART0 Block Diagram ....................................................................... 187
Figure 17.2. UART0 Baud Rate Logic.................................................................... 188
Figure 17.3. UART Interconnect Diagram .............................................................. 189
Figure 17.4. 8-Bit UART Timing Diagram............................................................... 189
Figure 17.5. 9-Bit UART Timing Diagram............................................................... 190
Figure 17.6. UART Multi-Processor Mode Interconnect Diagram .......................... 191
Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ....
194
18.Enhanced Serial Peripheral Interface (SPI0)
Figure 18.1. SPI Block Diagram ............................................................................. 195
Figure 18.2. Multiple-Master Mode Connection Diagram....................................... 198
Figure 18.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 198
Figure 18.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
198
Figure 18.5. Master Mode Data/Clock Timing........................................................ 200
Figure 18.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 200
Figure 18.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 201
Figure 18.8. SPI Master Timing (CKPHA = 0)........................................................ 206
Figure 18.9. SPI Master Timing (CKPHA = 1)........................................................ 206
Figure 18.10. SPI Slave Timing (CKPHA = 0)........................................................ 207
Figure 18.11. SPI Slave Timing (CKPHA = 1)........................................................ 207
Table 18.1. SPI Slave Timing Parameters ............................................................. 208
19.Timers
Figure 19.1. T0 Mode 0 Block Diagram.................................................................. 210
Figure 19.2. T0 Mode 2 Block Diagram.................................................................. 211
Figure 19.3. T0 Mode 3 Block Diagram.................................................................. 212
Figure 19.4. Timer 2 16-Bit Mode Block Diagram .................................................. 217
Figure 19.5. Timer 2 8-Bit Mode Block Diagram .................................................... 218
Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)...................................... 219
Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)...................................... 219
Figure 19.8. Timer 3 16-Bit Mode Block Diagram .................................................. 222
Figure 19.9. Timer 3 8-Bit Mode Block Diagram .................................................... 223
Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’).................................... 224
Rev. 1.4 11
C8051F320/1
Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’).................................... 224
20.Programmable Counter Array (PCA0)
Figure 20.1. PCA Block Diagram............................................................................ 227
Table 20.1. PCA Timebase Input Options.............................................................. 228
Figure 20.2. PCA Counter/Timer Block Diagram.................................................... 228
Table 20.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..... 229
Figure 20.3. PCA Interrupt Block Diagram ............................................................. 230
Figure 20.4. PCA Capture Mode Diagram.............................................................. 231
Figure 20.5. PCA Software Timer Mode Diagram.................................................. 232
Figure 20.6. PCA High Speed Output Mode Diagram............................................ 233
Figure 20.7. PCA Frequency Output Mode ............................................................ 234
Figure 20.8. PCA 8-Bit PWM Mode Diagram ......................................................... 235
Figure 20.9. PCA 16-Bit PWM Mode...................................................................... 236
Figure 20.10. PCA Module 4 with Watchdog Timer Enabled ................................. 237
Table 20.3. Watchdog Timer Timeout Intervals
1 ...................................................................239
21.C2 Interface
Figure 21.1. Typical C2 Pin Sharing....................................................................... 247
C8051F320/1
12 Rev. 1.4
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . 46
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 47
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 50
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . 50
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 51
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 51
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 61
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 10.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 10.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 11.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 11.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 11.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SFR Definition 12.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 115
SFR Definition 13.1. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.2. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 121
SFR Definition 13.4. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 13.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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