C8051F320/1
88 Rev. 1.4
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bit
s in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “19.1. Timer 0 and Timer 1” on page 209) select level or
edge sensitive. The table below lists
the possible configurations.
Active low, edge sensitive Active low, edge sensitive
Active high, edge sensitive
Active high, edge sensi-
tive
Active low, level sensitive Active low, level sensitive
Active high, level sensitive Active high, level sensitive
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see Figure 9.13). Note that
/INT0 and /INT0 Port pin assignments are independent of any Cros
sbar
assignments. /INT0 and /INT1 will
monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected
pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “14.1. Priority
Crossbar Decoder” on page 128 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-
pen
ding flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-
sponding interrupt-pending flag is automatically cleared by th
e hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac-
tive. The external interrupt source must hold the input a
c
tive until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted b
y a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 9.4.
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
10 10
11 11
00 00
01 01
