Rev. 1.4 87
C8051F320/1
9.3. Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two prior-
ity levels. The allocation of inter
rupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interrupt-
pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request
is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service ro
utine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or di
sabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recogn
ized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: an
y instruction which clears the EA bit should be immediately followed by an instruction which has
two or more opcode bytes. For example:
// in 'C':
EA = 0; // clear EA bit
EA = 0; // ... followed by another 2-byte opcode
; in assembly:
CLR EA ; clear EA bit
CLR EA ; ... followed by another 2-byte opcode
If an interrupt is posted during the execution phase of
a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. If the
EA bit is read inside the interrupt service routine, it will return a '0'. When the "CLR EA" opcode is followed
by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared
by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
9.3.1. MCU Interrupt Sources and Vectors
The MCU supports 16 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic 1. If interrupts are enabled for the flag,
an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order and control bits are summarized in Table 9.4 on page 89. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
co
nditions for the peripheral and the behavior of its interrupt-pending flag(s).
