Rev. 1.4 73

C8051F320/1

9.1.2. MOVX Instruction and Program Memory

The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not

support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses

external RAM (XRAM) and the on-chip program memory space implemented as re-programmable Flash

memory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use

the program memory space for non-volatile data storage. Refer to Section “11. Flash Memory” on

page 106 for further details.

Table 9.1. CIP-51 Instruction Set Summary

Mnemonic Description Bytes

Clock

Cycles

Arithmetic Operations

ADD A, Rn Add register to A 1 1

ADD A, direct Add direct byte to A 2 2

ADD A, @Ri Add indirect RAM to A 1 2

ADD A, #data Add immediate to A 2 2

ADDC A, Rn Add register to A with carry 1 1

ADDC A, direct Add direct byte to A with carry 2 2

ADDC A, @Ri Add indirect RAM to A with carry 1 2

ADDC A, #data Add immediate to A with carry 2 2

SUBB A, Rn Subtract register from A with borrow 1 1

SUBB A, direct Subtract direct byte from A with borrow 2 2

SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2

SUBB A, #data Subtract immediate from A with borrow 2 2

INC A Increment A 1 1

INC Rn Increment register 1 1

INC direct Increment direct byte 2 2

INC @Ri Increment indirect RAM 1 2

DEC A Decrement A 1 1

DEC Rn Decrement register 1 1

DEC direct Decrement direct byte 2 2

DEC @Ri Decrement indirect RAM 1 2

INC DPTR Increment Data Pointer 1 1

MUL AB Multiply A and B 1 4

DIV AB Divide A by B 1 8

DA A Decimal adjust A 1 1

Logical Operations

ANL A, Rn AND Register to A 1 1

ANL A, direct AND direct byte to A 2 2

ANL A, @Ri AND indirect RAM to A 1 2

ANL A, #data AND immediate to A 2 2

ANL direct, A AND A to direct byte 2 2

ANL direct, #data AND immediate to direct byte 3 3

ORL A, Rn OR Register to A 1 1

ORL A, direct OR direct byte to A 2 2

ORL A, @Ri OR indirect RAM to A 1

ORL A, #data OR immediate to A 2 2

C8051F320/1

74 Rev. 1.4

ORL direct, A OR A to direct byte 2 2

ORL direct, #data OR immediate to direct byte 3 3

XRL A, Rn Exclusive-OR Register to A 1 1

XRL A, direct Exclusive-OR direct byte to A 2 2

XRL A, @Ri Exclusive-OR indirect RAM to A 1 2

XRL A, #data Exclusive-OR immediate to A 2 2

XRL direct, A Exclusive-OR A to direct byte 2 2

XRL direct, #data Exclusive-OR immediate to direct byte 3 3

CLR A Clear A 1 1

CPL A Complement A 1 1

RL A Rotate A left 1 1

RLC A Rotate A left through Carry 1 1

RR A Rotate A right 1 1

RRC A Rotate A right through Carry 1 1

SWAP A Swap nibbles of A 1 1

Data Transfer

MOV A, Rn Move Register to A 1 1

MOV A, direct Move direct byte to A 2 2

MOV A, @Ri Move indirect RAM to A 1 2

MOV A, #data Move immediate to A 2 2

MOV Rn, A Move A to Register 1 1

MOV Rn, direct Move direct byte to Register 2 2

MOV Rn, #data Move immediate to Register 2 2

MOV direct, A Move A to direct byte 2 2

MOV direct, Rn Move Register to direct byte 2 2

MOV direct, direct Move direct byte to direct byte 3 3

MOV direct, @Ri Move indirect RAM to direct byte 2 2

MOV direct, #data Move immediate to direct byte 3 3

MOV @Ri, A Move A to indirect RAM 1 2

MOV @Ri, direct Move direct byte to indirect RAM 2 2

MOV @Ri, #data Move immediate to indirect RAM 2 2

MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3

MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3

MOVC A, @A+PC Move code byte relative PC to A 1 3

MOVX A, @Ri Move external data (8-bit address) to A

1 3

MOVX @Ri, A Move A to external data (8-bit address) 1 3

MOVX A, @DPTR Move external data (16-bit address) to A 1 3

MOVX @DPTR, A Move A to external data (16-bit address) 1 3

PUSH direct Push direct byte onto stack 2 2

POP direct Pop direct byte from stack 2 2

XCH A, Rn Exchange Register with A 1 1

XCH A, direct Exchange direct byte with A 2 2

XCH A, @Ri Exchange indirect RAM with A 1 2

XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic Description Bytes

Clock

Cycles

Rev. 1.4 75

C8051F320/1

Boolean Manipulation

CLR C Clear Carry 1 1

CLR bit Clear direct bit 2 2

SETB C Set Carry 1 1

SETB bit Set direct bit 2 2

CPL C Complement Carry 1 1

CPL bit Complement direct bit 2 2

ANL C, bit AND direct bit to Carry 2 2

ANL C, /bit AND complement of direct bit to Carry 2 2

ORL C, bit OR direct bit to carry 2 2

ORL C, /bit OR complement of direct bit to Carry 2 2

MOV C, bit Move direct bit to Carry 2 2

MOV bit, C Move Carry to direct bit 2 2

JC rel Jump if Carry is set 2 2/3

JNC rel Jump if Carry is not set 2 2/3

JB bit, rel Jump if direct bit is set 3 3/4

JNB bit, rel Jump if direct bit is not set 3 3/4

JBC bit, rel Jump if direct bit is set and clear bit 3 3/4

Program Branching

ACALL addr11 Absolute subroutine call 2 3

LCALL addr16 Long subroutine call 3 4

RET Return from subroutine 1 5

RETI Return from interrupt 1 5

AJMP addr11 Absolute jump 2 3

LJMP addr16 Long jump 3 4

SJMP rel Short jump (relative address) 2 3

JMP @A+DPTR Jump indirect relative to DPTR 1 3

JZ rel Jump if A equals zero 2 2/3

JNZ rel Jump if A does not equal zero 2 2/3

CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/4

CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4

CJNE Rn, #data, rel

Compare immediate to Register and jump if not

ual

3 3/4

CJNE @Ri, #data, rel

Compare immediate to indirect and jump if not

ual

3 4/5

DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3

DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/4

NOP

No operation 1 1

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic Description Bytes

Clock

Cycles

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document