C8051F320/1
72 Rev. 1.4
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions
except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core execut
es 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a
to
tal of 109 instructions. The table below shows the total number of instructions that for execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via
the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
mable Flash can also be read and changed a single byte at a time
by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor-
age as well as updating program code under software control.
The on-chip debug support logic
facilit
ates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
ot
he
r on-chip resources. C2 details can be found in Section “21. C2 Interface” on page 245.
The CIP-51 is supported by devel
opment tools
from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including ed
itor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and e
fficient in-system device programming and debugging. Third party macro assemblers and C compil-
ers are also available.
9.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instr
uctions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most in
str
uctions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mn
emo
nic, number of bytes, and number of clock
cycles for each instruction.
