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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
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SILICON LABS
Date Code: 0603
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F320/1
58 Rev. 1.4
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis
-
abled, the Comparator output (if assigned to a Port I/O pin via the Cr
ossbar) defaults to the logic low state,
and supply current falls to less than 100 nA. See Section “14.1. Priority Crossbar Decoder” on page 128
for details on configuring Comparator outputs via the digita
l Crossbar. Comparator inputs can be externally
driven from –0.25 V to (V
DD
) + 0.25 V without damage or upset. The complete Comparator electrical spec-
ifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see Figure 7.3 and
Figure 7.6). Selecting a longer response time reduces the Comparator supply current. See Table 7.1 for
complete timing and supply current specifications.
VDD
CPT1CN
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
P1.2
P1.6
P2.2
P2.6
CP1 -
P1.3
P1.7
P2.3
P2.7
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CPT1MX
CMX1N1
CMX1N0
CMX1P1
CMX1P0
CPT1MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge
CP1
Falling-edge
CP1
Interrupt
CP1RIE
CP1FIE
Note: P2.6 and P2.7 available
only on C8051F320
Figure 7.2. Comparator1 Functional Block Diagram
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0-
CP0
VIN+
VIN-
OUT
V
OH
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
V
OL
Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPTnCN (shown
in Figure 7.1 and Figure 7.4). The amount of negative hysteresis volta
ge is determined by the settings of
the CPnHYN bits. As shown in Figure 7.3, settings of 20, 10 or 5 mV of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar
way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on
both
rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “9.3. Interrupt Handler” on page 87.) The CPnFIF flag is set to
‘1’ upon a Comparator falling-edge, and the CPnRIF flag
is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
Rev. 1.4 59
C8051F320/1
Figure 7.3. Comparator Hysteresis Plot
C8051F320/1
60 Rev. 1.4
SFR Definition 7.1. CPT0CN: Comparator0 Control
Bit7: CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6: CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5: CP0RIF: Comparator0 Rising-Edge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4: CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9B
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