Rev. 1.4 55

C8051F320/1

6. Voltage Reference

The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected volt-

age reference, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1).

The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal

ference or an external source, REFSL should be set to ‘0’; For VDD as the reference source, REFSL

should be set to ‘1’.

The BIASE bit enables the internal ADC bias

generator

, which is used by the ADC and Internal Oscillator.

This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias

generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see Figure 6.1 for

REF0CN register details. The Refe

nce bias generator (see Figure 6.1) is used by the Internal Voltage

Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically enabled when

y of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference

and bias circuits are given in Table 6.1.

Important Note About the VREF Input: Por

pin P0.7 is used as the external VREF input. When using an

external voltage reference, P0.7 should be configured as analog input and skipped by the Digital Crossbar.

To configure P0.7 as analog input, set to ‘0’ Bit7 in register P0MDIN. To configure the Crossbar to skip

P0.7, set to ‘1’ Bit7 in register P0SKIP. Refer to Section “14. Port Input/Output” on page 126 for complete

Port I/O configuration details.

The temperature sensor connects to the ADC

positive input multiplexer (see Section “5.1. Analog Multi-

plexer” on page 40 for details). The TEMPE bit in register REF0

CN enables/disables the temperature sen-

sor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0

measur

ements performed on the sensor result in meaningless data.

VREF

(to ADC)

To Analog Mux

VDD

VREF

VDD

External

Voltage

Reference

Circuit

GND

Temp Sensor

REF0CN

REFSL

TEMPE

BIASE

REFBE

Internal

Reference

Bias

CLKMUL

Enable

TEMPE

To Clock Multiplier,

Temp Sensor

ADC Bias

To ADC,

Internal Oscillator

IOSCEN

AD0EN

Figure 6.1. Voltage Reference Functional Block Diagram

C8051F320/1

56 Rev. 1.4

SFR Definition 6.1.

Bits7–3: UNUSED. Read = 00000b; Write = don’t care.

Bit3: REFSL: Voltage Reference Select.

This bit selects the source for the internal voltage reference.

0: VREF pin used as voltage reference.

1: VDD used as voltage reference.

Bit2: TEMPE: Temperature Sensor Enable Bit.

0: Internal Temperature Sensor off.

1: Internal Temperature Sensor on.

Bit1: BIASE: Internal Analog Bias Generator Enable Bit.

0: Internal Bias Generator off.

1: Internal Bias Generator on.

Bit0: REFBE: Internal Reference Buffer Enable Bit.

0: Internal Reference Buffer disabled.

1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - - - REFSL TEMPE BIASE REFBE 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xD1

REF0CN: Reference Control

Table 6.1. Voltage Reference Electrical Characteristics

= 3.0 V; –40 to +85 °C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Internal Reference (REFBE = 1)

Output Voltage 25 °C ambient 2.38 2.44 2.50 V

VREF Short-Circuit Current 10 mA

VREF Temperature Coeffi-

cient

15 ppm/°C

Load Regulation Load = 0 to 200 µA to GND 1.5 ppm/µA

VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic bypass 2 ms

VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs

VREF Turn-on Time 3 no bypass cap 10 µs

Power Supply Rejection 140 ppm/V

External Reference (REFBE = 0)

Input Voltage Range 0 VDD V

Input Current Sample Rate = 200 ksps; VREF = 3.0 V 12 µA

Bias Generators

ADC Bias Generator BIASE = ‘1’ 106 148 µA

Reference Bias Generator 42 60 µA

Rev. 1.4 57

C8051F320/1

7. Comparators

C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in

Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the follow-

ing exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can

be used as a reset source.

Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two

tputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an

asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system

clock is not active. This allows the Comparators to operate and generate an output with the device in

STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or

push-pull (see Section “14.2. Port I/O Initializa

ion” on page 130). Comparator0 may also be used as a

reset source (see Section “10.5. Comparator0 Reset” on page 102).

The Comparator0 inputs are selected in the CPT0MX register (Figure 7.2). The CMX0P1–CMX0P0 bits

select the Comparator0 positive input; the CMX0N1–CMX0N0 b

ts select the Comparator0 negative input.

The Comparator1 inputs are selected in the CPT1MX register (Figure 7.5). The CMX1P1–CMX1P0 bits

select the Comparator1 positive input; the CMX1N1–CMX1N

0 bits select the Comparator1 negative input.

Important Note About Comparator Inputs: The Por

t pins selected as Comparator inputs should be con-

figured as analog inputs in their associated Port configuration

Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O” on page 132).

VDD

CPT0CN

Reset

Decision

Tree

Crossbar

Interrupt

Logic

SET

CLR

SET

CLR

(SYNCHRONIZER)

GND

CP0 +

P1.0

P1.4

P2.0

P2.4

CP0 -

P1.1

P1.5

P2.1

P2.5

CP0EN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1

CP0HYP0

CP0HYN1

CP0HYN0

CPT0MX

CMX0N1

CMX0N0

CMX0P1

CMX0P0

CPT0MD

CP0RIE

CP0FIE

CP0MD1

CP0MD0

CP0

CP0A

CP0

Rising-edge

CP0

Falling-edge

CP0

Interrupt

CP0RIE

CP0FIE

Note: P2.4 and P2.5 available

only on C8051F320

Figure 7.1. Comparator0 Functional Block Diagram

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

Related Items

Technical Document