Rev. 1.4 49

C8051F320/1

SFR Definition 5.6.

Bit7: AD0EN: ADC0 Enable Bit.

0: ADC0 Disabled. ADC0 is in low-power shutdown.

1: ADC0 Enabled. ADC0 is active and ready for data conversions.

Bit6: AD0TM: ADC0 Track Mode Bit.

0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion

is in progress.

1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).

Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.

0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.

1: ADC0 has completed a data conversion.

Bit4: AD0BUSY: ADC0 Busy Bit.

Read:

0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set

to logic 1 on the falling edge of AD0BUSY.

1: ADC0 conversion is in progress.

Write:

0: No Effect.

1: Initiates ADC0 Conversion if AD0CM2–0 = 000b

Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.

0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.

1: ADC0 Window Comparison Data match has occurred.

Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.

When AD0TM = 0:

000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.

001: ADC0 conversion initiated on overflow of Timer 0.

010: ADC0 conversion initiated on overflow of Timer 2.

011: ADC0 conversion initiated on overflow of Timer 1.

100: ADC0 conversion initiated on rising edge of external CNVSTR.

101: ADC0 conversion initiated on overflow of Timer 3.

11x: Reserved.

When AD0TM = 1:

000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conver-

sion.

001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.

010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.

011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.

100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR

edge.

101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.

11x: Reserved.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

(bit addressable)

0xE8

ADC0CN: ADC0 Control

C8051F320/1

50 Rev. 1.4

5.4. Programmable Window Detector

The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-

programmed limits, and notifies the system when a desired condition is detected. This is especially effec-

tive in an interrupt-driven system, saving code space and CPU bandwidth while delivering fast

er system

response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in

polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)

registers hold the comparison values. The window detector flag can be programmed to indicate when mea-

sured data is inside or outside of the user-program

med

limits, depending on the contents of the ADC0

Less-Than and ADC0 Greater-Than registers.

The Window Detector registers must be written with the same

for

mat (left/right justified, signed/unsigned)

as that of the current ADC configuration (left/right justified, single-ended/differential).

SFR Definition 5.7.

Bits7–0: High byte of ADC0 Greater-Than Data Word.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC4

ADC0GTH: ADC0 Greater-Than Data High Byte

SFR Definition 5.8.

Bits7–0: Low byte of ADC0 Greater-Than Data Word.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

11111111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC3

ADC0GTL: ADC0 Greater-Than Data Low Byte

Rev. 1.4 51

C8051F320/1

SFR Definition 5.9.

Bits7–0: High byte of ADC0 Less-Than Data Word.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC6

ADC0LTH: ADC0 Less-Than Data High Byte

SFR Definition 5.10.

Bits7–0: Low byte of ADC0 Less-Than Data Word.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0xC5

ADC0LTL: ADC0 Less-Than Data Low Byte

Part #	C8051F321-GMR
Description	16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category	IC
Availability	In Stock
Qty	560

Qty	Price
1 - 24	$10.41286
25 - 60	$8.28296
61 - 128	$7.80964
129 - 275	$7.25745
276 +	$6.46859

C8051F321-GMR

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Technical Document