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C8051F321-GMR

Part # C8051F321-GMR
Description 16KB,10ADC,USB,28PIN MCU (LEAD FREE) MLP28 -40 TO 85 DEG.
Category IC
Availability In Stock
Qty 560
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25 - 60 $8.28296
61 - 128 $7.80964
129 - 275 $7.25745
276 + $6.46859
Manufacturer Available Qty
SILICON LABS
Date Code: 0603
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Rev. 1.4 37
C8051F320/1
Figure 4.5. QFN-28 Package Drawing
Table 4.4. QFN-28 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 0.80 0.90 1.00 L 0.35 0.55 0.65
A1 0.00 0.02 0.05 L1 0.00 0.15
A3 0.25 REF aaa 0.15
b 0.18 0.23 0.30 bbb 0.10
D 5.00 BSC. ddd 0.05
D2 2.90 3.15 3.35 eee 0.08
e 0.50 BSC. Z 0.44
E 5.00 BSC. Y 0.18
E2 2.90 3.15 3.35
Notes:
1. Al
l dimensions shown are in millimeters (mm) unless otherwise noted.
2. D
imensioning and Tolerancing per ANSI Y14.5M-1994.
3. This draw
ing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. R
ecommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F320/1
38 Rev. 1.4
Figure 4.6. QFN-28 Recommended PCB Land Pattern
Table 4.5. QFN-28 PCB Land Pattern Dimesions
Dimension Min Max Dimension Min Max
C1 4.80 X2 3.20 3.30
C2 4.80 Y1 0.85 0.95
E 0.50 Y2 3.20 3.30
X1 0.20 0.30
Notes:
General
1. Al
l dimensions shown are in millimeters (mm) unless otherwise noted.
2. D
imensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. T
his Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. Al
l metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
5. A st
ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thic
kness should be 0.125mm (5 mils).
7. T
he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.9
0mm openings on a 1.1mm pitch should be used for the center pad to
assure the proper paste volume (67% Paste Coverage).
Card Assembly
9. A No-Cl
ean, Type-3 solder paste is recommended.
10. T
he recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.4 39
C8051F320/1
5. 10-Bit ADC (ADC0)
The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as
AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-
register ADC with
integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and
window detector are all configurable under software control via the Special Function Registers shown in
Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to mea-
sure P1.0-P3.0, the Temperature Sensor output, or VDD with respec
t to P1.0-
P3.0, VREF, or GND. The
ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to
logic 1. The ADC0 subsystem is in low power shutdow
n when this bit is logic 0.
ADC0CF
AD0LJST
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
19-to-1
AMUX
AD0WINT
001
010
011
100
CNVSTR Input
Window
Compare
Logic
GND
P1.0
P1.7
P2.0
P2.7
P3.0
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AMX0P
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AMX0N
AMX0N4
AMX0N3
AMX0N2
AMX0N1
AMX0N0
(+)
(-)
VREF
P2.4-2.7
available on
C8051F320
Temp
Sensor
19-to-1
AMUX
P1.0
P1.7
P2.0
P2.7
P3.0
P2.4-2.7
available on
C8051F320
VDD
Figure 5.1. ADC0 Functional Block Diagram
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