ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 4 of 24

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width

PW 1000 ns C

= 15 pF, CMOS signal levels

Maximum Data Rate

1 Mbps C

= 15 pF, CMOS signal levels

Propagation Delay

PHL

, t

PLH

50 65 100 ns C

= 15 pF, CMOS signal levels

Pulse-Width Distortion, |t

PLH

– t

PHL

PWD 40 ns C

= 15 pF, CMOS signal levels

Propagation Delay Skew

PSK

50 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching

PSKCD/OD

50 ns C

= 15 pF, CMOS signal levels

ADuM140xBRW

Minimum Pulse Width

PW 100 ns C

= 15 pF, CMOS signal levels

Maximum Data Rate

10 Mbps C

= 15 pF, CMOS signal levels

Propagation Delay

PHL

, t

PLH

20 32 50 ns C

= 15 pF, CMOS signal levels

Pulse-Width Distortion, |t

PLH

– t

PHL

PWD 3 ns C

= 15 pF, CMOS signal levels

Change vs. Temperature 5 ps/°C C

= 15 pF, CMOS signal levels

Propagation Delay Skew

PSK

15 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

PSKCD

3 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing-Directional Channels

PSKOD

6 ns C

= 15 pF, CMOS signal levels

ADuM140xCRW

Minimum Pulse Width

PW 8.3 11.1 ns C

= 15 pF, CMOS signal levels

Maximum Data Rate

90 120 Mbps C

= 15 pF, CMOS signal levels

Propagation Delay

PHL

, t

PLH

18 27 32 ns C

= 15 pF, CMOS signal levels

Pulse-Width Distortion, |t

PLH

– t

PHL

PWD 0.5 2 ns C

= 15 pF, CMOS signal levels

Change vs. Temperature 3 ps/°C C

= 15 pF, CMOS signal levels

Propagation Delay Skew

PSK

10 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels

PSKCD

2 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Opposing-Directional Channels

PSKOD

5 ns C

= 15 pF, CMOS signal levels

For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)

PHZ

, t

PLH

6 8 ns C

= 15 pF, CMOS signal levels

Output Enable Propagation Delay

(High Impedance to High/Low)

PZH

, t

PZL

6 8 ns C

= 15 pF, CMOS signal levels

Output Rise/Fall Time (10% to 90%) t

2.5 ns C

= 15 pF, CMOS signal levels

Common-Mode Transient Immunity

at Logic High Output

|CM

| 25 35 kV/µs

= V

DD1

DD2

, V

= 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity

at Logic Low Output

|CM

| 25 35 kV/µs

= 0 V, V

= 1000 V,

transient magnitude = 800 V

Refresh Rate f

1.2 Mbps

Input Dynamic Supply Current, per Channel

DDI (D)

0.19 mA/Mbps

Output Dynamic Supply Current, per Channel

DDO (D)

0.05 mA/Mbps

See Notes on next page.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 5 of 24

All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on

Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See

through for total I

Figure 8

Figure 10

Figure 11

Figure 14

DD1

and I

DD2

supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

PHL

propagation delay is measured from the 50% level of the falling edge of the V

signal to the 50% level of the falling edge of the V

signal. t

PLH

propagation delay is

measured from the 50% level of the rising edge of the V

signal to the 50% level of the rising edge of the V

signal.

PSK

is the magnitude of the worst-case difference in t

PHL

or t

PLH

that is measured between units at the same operating temperature, supply voltages, and output load

within the recommended operating conditions.

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

is the maximum common-mode voltage slew rate that can be sustained while maintaining V

> 0.8 V

DD2

. CM

is the maximum common-mode voltage slew rate

that can be sustained while maintaining V

< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information

on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel sup-

ply current for a given data rate.

Power Consumption

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 6 of 24

ELECTRICAL CHARACTERISTICS—3 V OPERATION

2.7 V ≤ V

DD1

≤ 3.6 V, 2.7 V ≤ V

DD2

≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-

wise noted; all typical specifications are at T

= 25°C, V

DD1

= V

DD2

= 3.0 V.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent I

DDI (Q)

0.26 0.31 mA

Output Supply Current, per Channel, Quiescent I

DDO (Q)

0.11 0.14 mA

ADuM1400, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

Supply Current I

DD1 (Q)

1.2 1.9 mA DC to 1 MHz logic signal freq.

DD2

Supply Current I

DD2 (Q)

0.5 0.9 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

DD1

Supply Current I

DD1 (10)

4.5 6.5 mA 5 MHz logic signal freq.

DD2

Supply Current I

DD2 (10)

1.4 2.0 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

DD1

Supply Current I

DD1 (90)

42 65 mA 45 MHz logic signal freq.

DD2

Supply Current I

DD2 (90)

11 15 mA 45 MHz logic signal freq.

ADuM1401, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

Supply Current I

DD1 (Q)

1.0 1.6 mA DC to 1 MHz logic signal freq.

DD2

Supply Current I

DD2 (Q)

0.7 1.2 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

DD1

Supply Current I

DD1 (10)

3.7 5.4 mA 5 MHz logic signal freq.

DD2

Supply Current I

DD2 (10)

2.2 3.0 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

DD1

Supply Current I

DD1 (90)

34 52 mA 45 MHz logic signal freq.

DD2

Supply Current I

DD2 (90)

19 27 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels

DC to 2 Mbps

DD1

or V

DD2

Supply Current I

DD1 (Q)

, I

DD2 (Q)

0.9 1.5 mA DC to 1 MHz logic signal freq.

10 Mbps (BRW and CRW Grades Only)

DD1

or V

DD2

Supply Current I

DD1 (10)

, I

DD2 (10)

3.0 4.2 mA 5 MHz logic signal freq.

90 Mbps (CRW Grade Only)

DD1

or V

DD2

Supply Current I

DD1 (90)

, I

DD2 (90)

27 39 mA 45 MHz logic signal freq.

For All Models

Input Currents

, I

IC,

, I

–10 +0.01 +10 µA

0 ≤ V

, V

≤ V

DD1

DD2

, 0 ≤ V

≤ V

DD1

or V

DD2

Logic High Input Threshold

, V

1.6 V

Logic Low Input Threshold

, V

0.4 V

DD1

, V

DD2

– 0.1 3.0 V I

= –20 µA, V

= V

IxH

Logic High Output Voltages

OAH

, V

OBH

OCH

, V

ODH

DD1

, V

DD2

– 0.4 2.8 V I

= –4 mA, V

= V

IxH

0.0 0.1 V I

= 20 µA, V

= V

IxL

0.04 0.1 V I

= 400 µA, V

= V

IxL

Logic Low Output Voltages

OAL

, V

OBL

OCL

, V

ODL

0.2 0.4 V I

= 4 mA, V

= V

IxL

SWITCHING SPECIFICATIONS

ADuM140xARW

Minimum Pulse Width

PW 1000 ns C

= 15 pF, CMOS signal levels

Maximum Data Rate

1 Mbps C

= 15 pF, CMOS signal levels

Propagation Delay

PHL

, t

PLH

50 75 100 ns C

= 15 pF, CMOS signal levels

Pulse-Width Distortion, |t

PLH

– t

PHL

PWD 40 ns C

= 15 pF, CMOS signal levels

Propagation Delay Skew

PSK

50 ns C

= 15 pF, CMOS signal levels

Channel-to-Channel Matching

PSKCD/OD

50 ns C

= 15 pF, CMOS signal levels

Part #	ADUM1401BRW
Description	Digital Isolator CMOS 4-Channel 10Mbps 16-Pin SOIC
Category	IC
Availability	Out of Stock
Qty	0

ADUM1401BRW

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