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AD8606AR

Part # AD8606AR
Description OP Amp Dual GP R-R I/O 5.5V 8-Pin SOIC N Tube - Rail/Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD8605/AD8606/AD8608
Rev. D | Page 16 of 20
I-V CONVERSION APPLICATIONS
PHOTODIODE PREAMPLIFIER APPLICATIONS
The low offset voltage and input current of the AD8605 make it
an excellent choice for photodiode applications. In addition, the
low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.
R
D
I
D
C
D
50pF
AD8605
V
OUT
PHOTODIODE
+VOS–
R
F
10M
C
F
10pF
02731-D-051
Figure 51. Equivalent Circuit for Photodiode Preamp
The input bias current of the amplifier contributes an error
term that is proportional to the value of R
F
.
The offset voltage causes a dark current induced by the shunt
resistance of the diode R
D
. These error terms are combined at
the output of the amplifier. The error voltage is written as
BF
D
F
OSO
IR
R
R
VE +
+= 1
Typically, R
F
is smaller than R
D
, thus R
F
/R
D
can be ignored.
At room temperature, the AD8605 has an input bias current of
0.2 pA and an offset voltage of 100 µV. Typical values of R
D
are
in the range of 1 GΩ.
For the circuit shown in Figure 9, the output error voltage is
approximately 100 µV at room temperature, increasing to about
1 mV at 85°C.
Where f
t
is the unity gain frequency of the amplifier, the
maximum achievable signal bandwidth is
T
F
t
MAX
CR
f
f
π
=
2
AUDIO AND PDA APPLICATIONS
The AD8605’s low distortion and wide dynamic range make it a
great choice for audio and PDA applications, including
microphone amplification and line output buffering.
Figure 52 shows a typical application circuit for headphone/line
out amplification.
R1 and R2 are used to bias the input voltage at half the supply.
This maximizes the signal bandwidth range. C1 and C2 are used
to ac couple the input signal. C1 and R2 form a high-pass filter
whose corner frequency is 1/2πR1C1.
The high output current of the AD8605 allows it to drive heavy
resistive loads.
The circuit of Figure 52 was tested to drive a 16 W headphone.
The THD + N is maintained at approximately −60 dB
throughout the audio range.
5V
4
2
3
8
1
HEADPHONES
5V
4
6
5
8
7
C1
1µF
R1
10k
R2
10k
V1
500mV
1/2
AD8606
C3
100µF
R4
20
R3
1k
1/2
AD8606
C4
100µF
R6
20
R5
1k
C2
1µF
V2
500mV
02731-D-052
Figure 52. Single-Supply Headphone/Speaker Amplifier
AD8605/AD8606/AD8608
Rev. D | Page 17 of 20
INSTRUMENTATION AMPLIFIERS
The low offset voltage and low noise of the AD8605 make it a
great amplifier for instrumentation applications.
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio.
Figure 53 shows a simple difference amplifier. The CMRR of the
circuit is plotted versus frequency. Figure 54 shows the
common-mode rejection for a unity gain configuration and for
a gain of 10.
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
AD8605
5V
V2
V1
R1
1k
R3
1k
R2
10k
R4
10k
V
OUT
R4
R3
R2
R1
=
V
OUT
= (V2–V1)
R2
R1
02731-D-053
Figure 53. Difference Amplifier, A
V
= 10
FREQUENCY (Hz)
120
100
0
100 10M1k
CMRR (dB)
10k 100k 1M
60
40
20
80
A
V
= 10
V
SY
= ±2.5V
A
V
= 1
02731-D-054
Figure 54. Difference Amplifier CMRR vs. Frequency
D/A CONVERSION
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
R2
AD8605
V
OS
R
F
C
F
R2 R2
V+
V–
02731-D-055
RRR
V
REF
Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
from the pole introduced by the output capacitance of the DAC.
Typical values for C
F
are in the range of 10 pF to 30 pF; it can be
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by the formula:
+=
q
R
VE
F
OSO
Re
1
where Req is the equivalent resistance seen at the output of the
DAC. As mentioned above, Req is code dependant and varies
with the input. A typical value for Req is 15 kΩ. Choosing a
feedback resistor of 10 kΩ yields an error of less than 200 µV.
Figure 56 shows the implementation of a dual-stage buffer at
the output of a DAC. The first stage is used as a buffer.
Capacitor C1, with Req, creates a low-pass filter and thus
provides phase lead to compensate for frequency response. The
second stage of the AD8606 is used to provide voltage gain at
the output of the buffer.
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
R
FB
V
DD
DB11
OUT1
AD7545
AGND
R
CS
R
P
V
IN
15V
V
OUT
V
REF
1/2
AD8606
1/2
AD8606
R4
5k10%
R1
10k
R2
10k
R3
20k
C1
33pF
02731-D-056
Figure 56. Bipolar Operation
AD8605/AD8606/AD8608
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
PIN 1
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
1
3
4 5
2
0.22
0.08
10°
0.50
0.30
0.15 MAX
SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
× 45°
Figure 58. 14-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-14)
0.80
0.60
0.40
4
85
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARIT
Y
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
4.50
4.40
4.30
14
8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
SEATING
PLANE
0.50 REF
0.87
0.37
0.36
0.35
0.17
0.14
0.12
0.21
0.50
0.20
0.50
0.23
0.18
0.14
BOTTOM VIEW
0.94
0.90
0.86
1.33
1.29
1.25
TOP VIEW
(BALL SIDE DOWN)
PIN 1
IDENTIFIE
Figure 62. 5-Bump 2 × 1 × 2 Array MicroCSP [WLCSP] (CB-5)
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