AMD
P R E L I M I N A R Y
2
Am79C970A
The PCnet-PCI II controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a DMA buffer management unit, an IEEE
802.3-compliant Media Access Control (MAC) function,
individual 272-byte transmit and 256-byte receive
FIFOs, an IEEE 802.3-compliant Attachment Unit
Interface (AUI) and Twisted-Pair Transceiver Media
Attachment Unit (10BASE-T MAU) that can both
operate in either half-duplex or full-duplex mode.
The PCnet-PCI II controller is register compatible with
the LANCE (Am7990) Ethernet controller, the
C-LANCE (Am79C90) Ethernet controller, the ILACC
(Am79C900) Ethernet controller, and all Ethernet
controllers in the PCnet Family, including the
PCnet-ISA controller (Am79C960), PCnet-ISA+
controller (Am79C961), PCnet-ISA II controller
(Am79C961A), PCnet-32 controller (Am79C965),
PCnet-PCI controller (Am79970), and the PCnet-SCSI
controller (Am79C974). The buffer management unit
supports the C-LANCE, ILACC, and PCnet descriptor
software models. The PCnet-PCI II controller is
software compatible with the Novell
NE2100 and
NE1500 Ethernet adapter card architectures.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to PCI local bus applications, simplifying
the design of an Ethernet node in a PC system. The
PCnet-PCI II controller provides the complete interface
to an Expansion ROM, allowing add-on card designs
with only a single load per PCI bus interface pin. With its
built-in support for both little and big endian byte align-
ment, this controller also addresses proprietary non-PC
applications. The PCnet-PCI II controller’s
advanced CMOS design allows the bus interface to be
connected to either a 5 V or a 3.3 V signaling environ-
ment. Both NAND Tree and JTAG test interfaces
are provided.
The PCnet-PCI II controller supports automatic
configuration in the PCI configuration space. Additional
PCnet-PCI II configuration parameters, including the
unique IEEE physical address, can be read from an ex-
ternal non-volatile memory (Microwire EEPROM) im-
mediately following system reset.
The controller has the capability to automatically select
either the AUI port or the Twisted-Pair transceiver. Only
one interface is active at any one time. Both network in-
terfaces can be programmed to operate in either half-
duplex or full-duplex mode. The individual transmit and
receive FIFOs optimize system overhead, providing suf-
ficient latency during frame transmission and reception,
and minimizing intervention during normal network error
recovery. The integrated Manchester encoder/decoder
(MENDEC) eliminates the need for an external Serial In-
terface Adapter (SIA) in the system. The built-in General
Purpose Serial Interface (GPSI) allows the MENDEC to
be by-passed. In addition, the device
provides programmable on-chip LED drivers for trans-
mit, receive, collision, receive polarity, link integrity, ac-
tivity, or jabber status. The PCnet-PCI II controller also
provides an External Address Detection Interface
(EADI) to allow fast external hardware address filtering
in internetworking applications.
For power sensitive applications where low stand-by
current is desired, the device incorporates two Sleep
functions to reduce over-all system power consumption,
excellent for notebooks and Green PCs. In conjunction
with these low power modes, the PCnet-PCI II controller
also has integrated functions to support Magic Packet,
an inexpensive technology that allows remote wake up
of Green PCs.
