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ADUM1200ARZ

Part # ADUM1200ARZ
Description DUAL-CHANNEL DIGITAL ISOLATORS 2.5KV 8PIN SOIC
Category IC
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Technical Document


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ADuM1200/ADuM1201
Rev. B | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 50 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
− t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
ADuM120xCR
Minimum Pulse Width
2
PW 20 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 50 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 45 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
– t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current, per Channel
8
I
DDI (D)
0.19 mA/Mbps
Output Dynamic Supply Current, per Channel
8
I
DDO (D)
0.05 mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11
for total I
Figure 8
Figure 8
Figure 9
DD1
and I
DD2
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply
current for a given data rate.
Figure 6
Power Consumption
ADuM1200/ADuM1201
Rev. B | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V. All min/max specifications apply over the
entire recommended operating range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.0 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent I
DDI (Q)
0.26 0.35 mA
Output Supply Current, per Channel, Quiescent I
DDO (Q)
0.11 0.20 mA
ADuM1200, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
0.6 1.0 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.2 0.6 mA DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current I
DD1 (10)
2.2 3.4 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
0.7 1.1 mA 5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current I
DD1 (25)
5.2 7.7 mA 12.5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (25)
1.5 2.0 mA 12.5 MHz logic signal freq.
ADuM1201, Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
0.4 0.8 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.4 0.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
V
DD1
Supply Current I
DD1 (10)
1.5 2.2 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
1.5 2.2 mA 5 MHz logic signal freq.
25 Mbps (CR Grade Only)
V
DD1
Supply Current I
DD1 (25)
3.4 4.8 mA 12.5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (25)
3.4 4.8 mA 12.5 MHz logic signal freq.
For All Models
Input Currents I
IA
, I
IB
−10 0.01 10 µA 0 ≤ V
IA
, V
IB
, ≤ V
DD1
or V
DD2
Logic High Input Threshold V
IH
0.7 V
DD1,
V
DD2
V
Logic Low Input Threshold V
IL
0.3 V
DD1
, V
DD2
Logic High Output Voltages V
OAH
V
DD1
,
V
DD2
− 0.1
3.0 V I
Ox
= −20 µA, V
Ix
= V
IxH
V
OBH
V
DD1
,
V
DD2
− 0.5
2.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
Logic Low Output Voltages V
OAL
0.0 0.1 V I
Ox
= 20 µA, V
Ix
= V
IxL
V
OBL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM120xAR
Minimum Pulse Width
2
PW 1000 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
50 150 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
− t
PHL
|
4
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
100 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
10 ns C
L
= 15 pF, CMOS signal levels
ADuM1200/ADuM1201
Rev. B | Page 6 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 60 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
−t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
22 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
3.0 ns C
L
= 15 pF, CMOS signal levels
ADuM120xCR
Minimum Pulse Width
2
PW 20 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 50 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 55 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
− t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
16 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
16 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
3.0 ns C
L
= 15 pF, CMOS signal levels
For All Models
Common Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.1 Mbps
Input Dynamic Supply Current, per Channel
8
I
DDI (D)
0.10 mA/Mbps
Output Dynamic Supply Current, per Channel
8
I
DDO (D)
0.03 mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure through Figure 11
for total I
Figure 8
Figure 8
9
DD1
and I
DD2
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply
current for a given data rate.
Figure 6
Power Consumption
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