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ADG406BN

Part # ADG406BN
Description Analog Multiplexer Single 16:1 28-Pin PDIP W Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

–4–
ADG406/ADG407/ADG426
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model Temperature Range Package Option*
ADG406BN –40°C to +85°C N-28
ADG406BP –40°C to +85°C P-28A
ADG407BN –40°C to +85°C N-28
ADG407BP –40°C to +85°C P-28A
ADG426BN –40°C to +85°C N-28
ADG426BRS –40°C to +85°C RS-28
*N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small
Outline Package (SSOP).
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs
2
. . . . . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V
or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
PLCC Package
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.
2
Overvoltages at A, S, D, WR or RS will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
–5–
REV. 0
ADG406/ADG407/ADG426
Table III. Truth Table (ADG426)
A3 A2 A1 A0 EN WR RS ON SWITCH
XXXXX 1 Retains Previous
Switch Condition
XXXXXX0 NONE (Address
and Enable
Latches Cleared)
XXXX0 0 1 NONE
00001011
00011012
00101013
00111014
01001015
01011016
01101017
01111018
10001019
100110110
101010111
101110112
110010113
110110114
111010115
111110116
V
DD
NC
D
V
SS
S15
S14
S13
S6
S5
S4
NC
S16
S8
S7
S12 S3
S11 S2
S10 S1
S9 EN
GND A0
NC A1
A3 A2
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
821
920
10 19
1111
12 17
16
14 15
TOP VIEW
(Not to Scale)
ADG406
PLCC
PIN CONFIGURATIONS
DIP
V
DD
DB
DA
V
SS
S7B
S6B
S5B
S6A
S5A
S4A
NC
S8B
S8A
S7A
S3A
S3B S2A
S2B S1A
S1B EN
GND A0
NC A1
NC A2
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
821
920
10 19
1111
12 17
16
14 15
TOP VIEW
(Not to Scale)
ADG407
S4B
PIN CONFIGURATION
DIP/SSOP
NC = NO CONNECT
V
DD
NC
D
V
SS
S15
S14
S13
S6
S5
S4
S16
S8
S7
S12 S3
S11 S2
S10 S1
S9 EN
GND A0
A1
A3 A2
13
18
1
2
28
27
5
6
7
24
23
22
3
4
26
25
821
920
10 19
1111
12 17
16
14
15
TOP VIEW
(Not to Scale)
ADG426
RS
WR
NC = NO CONNECT
S7
S6
S3
S2
S1
S5
S4
S15
S14
S11
S10
S9
S13
S12
S16
NC
D
V
SS
S8
NC
GND
NC
A1
A0
EN
A3
A2
V
DD
262728423
15 18171612 1413
25
24
21
20
19
23
22
TOP VIEW
(Not to Scale)
1
5
6
9
10
11
7
8
ADG406
Table I. Truth Table (ADG406)
A3 A2 A1 A0 EN ON SWITCH
XXXX0 NONE
000011
000112
001013
001114
010015
010116
011017
011118
100019
1001110
1010111
1011112
1100113
1101114
1110115
1111116
NC = NO CONNECT
S7A
S6A
S3A
S2A
S1A
S5A
S4A
S7B
S6B
S3B
S2B
S1B
S5B
S4B
S8B
NC
DA
V
SS
S8A
DB
GND
NC
A1
A0
EN
NC
A2
V
DD
262728423
15 18171612 1413
25
24
21
20
19
23
22
TOP VIEW
(Not to Scale)
1
5
6
9
10
11
7
8
ADG407
Table II. Truth Table (ADG407)
A2 A1 A0 EN ON SWITCH PAIR
XXX0 NONE
00011
00112
01013
01114
10015
10116
11017
11118
–6–
ADG406/ADG407/ADG426
REV. 0
TIMING DIAGRAMS (ADG426)
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while
WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of
WR.
Figure 2.
Figure 2 shows the Reset Pulse Width, t
RS
, and the Reset Turn
Off Time, t
OFF
(RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
R
= t
F
= 20 ns.
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
GND Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
R
ON
Match Difference between the R
ON
of any two
channels.
I
S
(OFF) Source leakage current when the switch is off.
I
D
(OFF) Drain leakage current when the switch is off.
I
D
, I
S
(ON) Channel leakage current when the switch
is on.
V
D
(V
S
) Analog voltage on terminals D, S.
C
S
(OFF) Channel input capacitance for “OFF”
condition.
C
D
(OFF) Channel output capacitance for “OFF”
condition.
C
D
, C
S
(ON) “ON” switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN) Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
t
OFF
(EN) Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
t
TRANSITION
Delay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
t
OPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for logic “0.”
V
INH
Minimum input voltage for logic “1.”
I
INL
(I
INH
) Input current of the digital input.
Crosstalk A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” channel.
Charge A measure of the glitch impulse
Injection transferred from the digital input to the analog
output during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
50%
t
W
50%
t
S
2V
0.8V
t
H
3V
WR
0V
3V
A0, A1, A2, (A3)
EN
0V
50%
t
RS
50%
0.8V
0
3V
0V
V
0
0V
RS
t
OFF
(RS )
SWITCH
OUTPUT
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