Applying the AD840
REV. C
–7–
Figure 24 shows the “long-term” stability of the settling charac-
teristics of the AD840 output after a 10 V step. There is no evi-
dence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful lay-
out, avoids these problems by minimizing the effects of transis-
tor isolation capacitance discharge and thermally induced shifts
in circuit operating points. These problems do not occur even
under high output current conditions.
Figure 24. AD840 Settling Demonstrating No Settling Tails
GROUNDING AND BYPASSING
In designing practical circuits with the AD840, the user must re-
member that whenever high frequencies are involved, some spe-
cial precautions are in order. Circuits must be built with short
interconnect leads. Large ground planes should be used when-
ever possible to provide a low resistance, low inductance circuit
path, as well as minimizing the effects of high frequency cou-
pling. Sockets should be avoided, because the increased
inter-lead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a small
(±10 pF) feedback capacitor in connected parallel with the feed-
back resistor, R
F
, may be used to compensate for these stray ca-
pacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 µF capacitor in parallel with
a 0.1 µF ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD840 is sensitive to capaci-
tive loading. The AD840 is designed to drive capacitive loads
of up to 20 pF without degradation of its rated performance.
Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF. A resistor in series with the out-
put can be used to decouple larger capacitive loads.
USING A HEAT SINK
The AD840 draws less quiescent power than most high speed
amplifiers and is specified for operation without a heat sink.
However, when driving low impedance loads the current to the
load can be 4 to 5 times the quiescent current. This will create a
noticeable temperature rise. Improved performance can be
achieved by using a small heat sink such as the Aavid Engineer-
ing #602B.
AD840 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD840
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which com-
prise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output
value; (3) the time of recovery from the overload associated with
slewing; and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
Figure 22. AD840 0.01% Settling Time
TEK
7A13
TEK
7A18
TEK
7603
OSCILLOSCOPE
ERROR
AMP
(x11)
DDD5109
FLAT-TOP
PULSE
GENERATOR
5
4
11
10
6
2.2µF
0.1µF
+15V
FET PROBE
TEK P6201
499
4.99k
50
AD840
4.99k
0.1µF
2.2µF
499
499
-15V
HP6263
499
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD840’s 0.01% set-
tling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high speed propri-
etary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
420 Ω load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp amplifies the
error from the false summing junction by 11, and it contains a
gain vernier to fine trim the gain.
