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AD8402AN100

Part # AD8402AN100
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
1-/2-/4-Channel
Digital Potentiometers
AD8400/AD8402/AD8403
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
FEATURES
256 Position
Replaces 1, 2 or 4 Potentiometers
1 kV, 10 kV, 50 kV, 100 kV
Power Shut Down—Less than 5 mA
3-Wire SPI Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single-Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
FUNCTIONAL BLOCK DIAGRAM
RDAC1
SHDN
8
8-BIT
LATCH
CK
RS
RDAC2
SHDN
8
8-BIT
LATCH
CK
RS
RDAC3
SHDN
8
8-BIT
LATCH
CK
RS
RDAC4
SHDN
8
8-BIT
LATCH
CK
RS
SHDN
DAC
SELECT
A1, A0
1
2
3
4
10-BIT
SERIAL
LATCH
CK Q RS
D
RS
SDO
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
AD8403
V
DD
DGND
SDI
CLK
CS
8
2
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single, dual or quad
channel, 256 position digitally controlled variable resistor (VR)
device. These devices perform the same electronic adjustment
function as a potentiometer or variable resistor. The AD8400
contains a single variable resistor in the compact SO-8 package.
The AD8402 contains two independent variable resistors in
space saving SO-14 surface mount package. The AD8403 con-
tains four independent variable resistors in 24-lead PDIP, SOIC
and TSSOP packages. Each part contains a fixed resistor with a
wiper contact that taps the fixed resistor value at a point deter-
mined by a digital code loaded into the controlling serial input
register. The resistance between the wiper and either endpoint
of the fixed resistor varies linearly with respect to the digital
code transferred into the VR latch. Each variable resistor offers
a completely programmable value of resistance, between the A
terminal and the wiper or the B terminal and the wiper. The
fixed A to B terminal resistance of 1 k, 10 k, 50 k or 100 k
has a ±1% channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching cir-
cuit minimizes the high glitch inherent in traditional switched
resistor designs avoiding any make-before-break or break-before-
make operation.
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPI
compatible serial-to-parallel shift register that is loaded from a
standard 3-wire serial-input digital interface. Ten data bits make
up the data word clocked into the serial input register. The data
word is decoded where the first two bits determine the address
of the VR latch to be loaded, the last eight bits are data. A serial
data output pin at the opposite end of the serial register allows
simple daisy-chaining in multiple VR applications without addi-
tional external decoding logic.
The reset (
RS) pin forces the wiper to the midscale position by
loading 80
H
into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on the A terminal
and shorts the wiper to the B terminal, achieving a microwatt
power shutdown state. When
SHDN is returned to logic high,
the previous latch settings put the wiper in the same resistance
setting prior to shutdown. The digital interface is still active in
shutdown so that code changes can be made which will produce
new wiper positions when the device is taken out of shutdown.
The AD8400 is available in both the SO-8 surface mount and
the 8-lead plastic DIP package.
The AD8402 is available in both surface mount (SO-14) and
the 14-lead plastic DIP package, while the AD8403 is available
in a narrow body 24-lead plastic DIP and the 24-lead surface
mount package. The AD8402/AD8403 are also offered in the
1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap-
plications. All parts are guaranteed to operate over the extended
industrial temperature range of –40°C to +85°C.
10 kV VERSION
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
= NC –1 ±1/4 +1 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
= NC –2 ±1/2 +2 LSB
Nominal Resistance
3
RT
A
= +25°C, Model: AD840XYY10 8 10 12 k
Resistance Tempco R
AB
/TV
AB
= V
DD
, Wiper = No Connect 500 ppm/°C
Wiper Resistance R
W
I
W
= 1 V/R 50 100
Nominal Resistance Match R/R
O
CH 1 to 2, 3, or 4,
V
AB
= V
DD
, T
A
= +25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution N 8 Bits
Integral Nonlinearity
4
INL –2 ±1/2 +2 LSB
Differential Nonlinearity
4
DNL V
DD
= +5 V –1 ±1/4 +1 LSB
DNL V
DD
= +3 V T
A
= +25°C–1±1/4 +1 LSB
DNL V
DD
= +3 V T
A
= –40°C, +85°C –1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco V
W
/T Code = 80
H
15 ppm/°C
Full-Scale Error V
WFSE
Code = FF
H
–4 –2.8 0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +1.3 +2 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
0V
DD
V
Capacitance
6
Ax, Bx C
A, B
f = 1 MHz, Measured to GND, Code = 80
H
75 pF
Capacitance
6
Wx C
W
f = 1 MHz, Measured to GND, Code = 80
H
120 pF
Shutdown Current
7
I
A_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance R
W_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= +5 V 100 200
DIGITAL INPUTS & OUTPUTS
Input Logic High V
IH
V
DD
= +5 V 2.4 V
Input Logic Low V
IL
V
DD
= +5 V 0.8 V
Input Logic High V
IH
V
DD
= +3 V 2.1 V
Input Logic Low V
IL
V
DD
= +3 V 0.6 V
Output Logic High V
OH
R
L
= 1 k to V
DD
V
DD
–0.1 V
Output Logic Low V
OL
I
OL
= 1.6 mA, V
DD
= +5 V 0.4 V
Input Current I
IL
V
IN
= 0 V or +5 V, V
DD
= +5 V ±1 µA
Input Capacitance
6
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 5 µA
Supply Current (TTL)
8
I
DD
V
IH
= 2.4 V or 0.8 V, V
DD
= +5.5 V 0.9 4 mA
Power Dissipation (CMOS)
9
P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 27.5 µW
Power Supply Sensitivity PSS V
DD
= +5 V ± 10% 0.0002 0.001 %/%
PSS V
DD
= +3 V ± 10% 0.006 0.03 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_10K R = 10 k 600 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz 0.003 %
V
W
Settling Time t
S
V
A
= V
DD
, V
B
= 0 V, ±1% Error Band 2 µs
Resistor Noise Voltage e
NWB
R
WB
= 5 k, f = 1 kHz, RS = 0 9 nV/Hz
Crosstalk
11
C
T
V
A
= V
DD
, V
B
= 0 V –65 dB
NOTES FOR 10 k VERSION
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
I
W
= 50 µA for V
DD
= +3 V and I
W
= 400 µA for V
DD
= +5 V for the 10 k versions.
3
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
DD
versus logic voltage.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
AD8400/AD8402/AD8403–SPECIFICATIONS
(V
DD
= +3 V 6 10% or + 5 V 6 10%, V
A
= +V
DD
, V
B
= 0 V, –408C T
A
+858C unless
otherwise noted)
REV. B
–2–
50 kV & 100 kV VERSION
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ
1
Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL R
WB
, V
A
= NC –1 ±1/4 +1 LSB
Resistor Nonlinearity
2
R-INL R
WB
, V
A
= NC –2 ±1/2 +2 LSB
Nominal Resistance
3
RT
A
= +25°C, Model: AD840XYY50 35 50 65 k
RT
A
= +25°C, Model: AD840XYY100 70 100 130 k
Resistance Tempco R
AB
/TV
AB
= V
DD
, Wiper = No Connect 500 ppm/°C
Wiper Resistance R
W
I
W
= 1 V/R 53 100
Nominal Resistance Match R/R
O
CH 1 to 2, 3, or 4,
V
AB
= V
DD
, T
A
= +25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution N 8 Bits
Integral Nonlinearity
4
INL –4 ±1 +4 LSB
Differential Nonlinearity
4
DNL V
DD
= +5 V –1 ±1/4 +1 LSB
DNL V
DD
= +3 V T
A
= +25°C–1±1/4 +1 LSB
DNL V
DD
= +3 V T
A
= –40°C, +85°C –1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco V
W
/T Code = 80
H
15 ppm/°C
Full-Scale Error V
WFSE
Code = FF
H
–1 –0.25 0 LSB
Zero-Scale Error V
WZSE
Code = 00
H
0 +0.1 +1 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
0V
DD
V
Capacitance
6
Ax, Bx C
A, B
f = 1 MHz, Measured to GND, Code = 80
H
15 pF
Capacitance
6
Wx C
W
f = 1 MHz, Measured to GND, Code = 80
H
80 pF
Shutdown Current
7
I
A_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance R
W_SD
V
A
= V
DD
, V
B
= 0 V, SHDN = 0, V
DD
= +5 V 100 200
DIGITAL INPUTS & OUTPUTS
Input Logic High V
IH
V
DD
= +5 V 2.4 V
Input Logic Low V
IL
V
DD
= +5 V 0.8 V
Input Logic High V
IH
V
DD
= +3 V 2.1 V
Input Logic Low V
IL
V
DD
= +3 V 0.6 V
Output Logic High V
OH
R
L
= 1 k to V
DD
V
DD
–0.1 V
Output Logic Low V
OL
I
OL
= 1.6 mA, V
DD
= +5 V 0.4 V
Input Current I
IL
V
IN
= 0 V or +5 V, V
DD
= +5 V ±1 µA
Input Capacitance
6
C
IL
5pF
POWER SUPPLIES
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 5 µA
Supply Current (TTL)
8
I
DD
V
IH
= 2.4 V or 0.8 V, V
DD
= +5.5 V 0.9 4 mA
Power Dissipation (CMOS)
9
P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 27.5 µW
Power Supply Sensitivity PSS V
DD
= +5 V ± 10% 0.0002 0.001 %/%
PSS V
DD
= +3 V ± 10% 0.006 0.03 %/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB BW_50K R = 50 k 125 kHz
BW_100K R = 100 k 71 kHz
Total Harmonic Distortion THD
W
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz 0.003 %
V
W
Settling Time t
S
_50K V
A
= V
DD
, V
B
= 0 V, ±1% Error Band 9 µs
t
S
_100K V
A
= V
DD
, V
B
= 0 V, ±1% Error Band 18 µs
Resistor Noise Voltage e
NWB
_50K R
WB
= 25 k, f = 1 kHz, RS = 0 20 nV/Hz
e
NWB
_100K R
WB
= 50 k, f = 1 kHz, RS = 0 29 nV/Hz
Crosstalk
11
C
T
V
A
= V
DD
, V
B
= 0 V –65 dB
NOTES FOR 50 k and 100 k VERSIONS
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
I
W
= V
DD
/R for V
DD
= +3 V or +5 V for the 50 k and 100 k versions.
3
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
DD
versus logic voltage.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
AD8400/AD8402/AD8403
REV. B
–3–
(V
DD
= +3 V 6 10% or + 5 V 6 10%, V
A
= +V
DD
, V
B
= 0 V, –408C T
A
+858C unless
otherwise noted)
SPECIFICATIONS
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