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AD8361ARM

Part # AD8361ARM
Description LF TO 2.5GHZ TRUPWR DETECTOR8MSOP - Rail/Tube
Category IC
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Analog Devices
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD8361
–13–
REV. A
The AD8361 can be disabled either by pulling the PWDN (Pin 4)
to VPOS or by simply turning off the power to the device. While
turning off the device obviously eliminates the current consump-
tion, disabling the device reduces the leakage current to less
than 1 µA. Figures 23 and 24 show the response of the output of
the AD8361 to a pulse on the PWDN pin, with no capacitance and
with a lter capacitance of 0.01 µF respectively; the turn-on time is
a function of the lter capacitor. Figure 27 shows a plot of the
output response to the supply being turned on (i.e., PWDN is
grounded and VPOS is pulsed) with a lter capacitor of 0.01 µF
Again, the turn-on time is strongly influenced by the size of the
lter capacitor.
If the input of the AD8361 is driven while the device is disabled
(PWDN = VPOS), the leakage current of less than 1 µA will
increase as a function of input level. When the device is dis-
abled, the output impedance increases to around 16 k.
Volts to dBm Conversion
In many of the plots, the horizontal axis is scaled in both rms
volts and dBm. In all cases, dBm are calculated relative to an
impedance of 50 . To convert between dBm and volts in a
50 . system, the following equations can be used. Figure 40
shows this conversion in graphical form.
Power dBm
V rms
W
V rms
V rms W
dBm
dBm
( ) log
()
.
log ( ( ) )
. log
log /
=
=
×
=
(
)
10
50
0 001
10 20
0 001 50
10
10
20
2
2
1
1
V rms dBm
+20
+10
0
10
20
30
40
1
0.1
0.01
0.001
Figure 41. Conversion from dBm to rms Volts
Output Drive Capability and Buffering
The AD8361 is capable of sourcing an output current of approxi-
mately 3 mA. If additional current is required, a simple buffering
circuit can be used as shown in Figure 42c. Similar circuits
can be used to increase or decrease the nominal conversion gain of
7.5 V/V rms (Figure 42a and 42b). In Figure 42b, the AD8031
buffers a resistive divider to give a slope of 3.75 V/V rms. In Figure
42a, the op amps gain of two increases the slope to 15 V/V rms.
Using other resistor values, the slope can be changed to an
arbitrary value. The AD8031 rail-to-rail op amp, used in these
examples can swing from 50 mV to 4.95 V on a single 5 V supply
and operate at supply voltages down to 2.7 V. If high output
current is required (>10 mA), the AD8051, which also has rail-
to-rail capability, can be used, down to a supply voltage of 3 V. It
can deliver up to 45 mA of output current.
100pF
0.01F
AD8361
VOUT
VPOS
COMM PWDN
5k
5k
0.01F
5V
15V/V rms
AD8031
a. Slope of 15 V/V rms
AD8361
VOUT
VPOS
COMM PWDN
0.01F
5V
3.75V/V rms
AD8031
10k
5k
5k
100pF
0.01F
b. Slope of 3.75 V/V rms
100pF
AD8361
VOUT
VPOS
COMM PWDN
0.01F
0.01F
5V
7.5V/V rms
AD8031
c. Slope of 7.5 V/V rms
Figure 42. Output Buffering Options
OUTPUT REFERENCE TEMPERATURE DRIFT
COMPENSATION
The error due to low temperature drift of the AD8361 can be
reduced if the temperature is known. Many systems incorporate
a temperature sensor; the output of the sensor is typically digi-
tized, facilitating a software correction. Using this information,
only a two-point calibration at ambient is required.
The output voltage of the AD8361 at ambient (25°C) can be
expressed by the equation:
V GAIN V V
OUT IN OS
()
+
where GAIN is the conversion gain in V/V rms and V
OS
is the
extrapolated output voltage for an input level of 0 V. GAIN and
V
OS
(also referred to as Intercept and Output Reference) can be
calculated at ambient using a simple two-point calibration;
that is, by measuring the output voltages for two specific input
levels. Calibration at roughly 35 mV rms (16 dBm) and
250 mV rms (+1 dBm) is recommended for maximum linear
dynamic range. However, alternative levels and ranges can be
AD8361
–14–
REV. A
chosen to suit the application. GAIN and V
OS
are then calculated
using the equations:
GAIN
VV
VV
OUT OUT
IN IN
=
()
()
21
21
V V GAIN V
OS OUT IN
=− ×
()
11
Both GAIN and V
OS
drift over temperature. However, the drift
of V
OS
has a bigger influence on the error relative to the output.
This can be seen by inserting data from Figures 14 and 17 (con-
version gain and intercept drift) into the equation for V
OUT
. These
plots are consistent with Figures 10 and 11 which show that the
error due to temperature drift decreases with increasing input
level. This results from the offset error having a diminishing
influence with increasing level on the overall measurement error.
From Figure 14, the average Intercept drift is 0.43 mV/°C from
40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a
less rigorous compensation scheme, the average drift over the
complete temperature range can be calculated:
DRIFT V C
VV
CC
VOS
/
..
°
()
=
−−
()
−°
()
0 010 0 028
85 40
= 0.000304 V/°C
With the drift of V
OS
included, the equation for V
OUT
becomes:
Table V. Evaluation Board Configuration Options
Component Function Default Condition
TP1, TP2 Ground and Supply Vector Pins. Not Applicable
SW1 Device Enable. When in Position A, the PWDN pin is connected to +V
S
and SW1 = B
the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded,
putting the device in operating mode.
SW2/SW3 Operating Mode. Selects either Ground Referenced Mode, Internal Reference SW2 = A, SW3 = B
Mode or Supply Reference Mode. See Table I for more details. (Ground Reference Mode)
C1, R2 Input Coupling. The 75 resistor in position R2 combines with the AD8361s R2 = 75 (Size 0402)
internal input impedance to give a broadband input impedance of around 50 . C1 = 100 pF (Size 0402)
For more precise matching at a particular frequency, R2 can be replaced by a
different value (see Input Matching and Figure 39).
Capacitor C1 ac-couples the input signal and creates a high-pass input lter
whose corner frequency is equal to approximately 8 MHz. C1 can be increased
for operation at lower frequencies. If resistive attenuation is desired at the input,
series resistor R1, which is nominally 0 , can be replaced by an appropriate value.
C2, C3, R6 Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and C2 = 0.01 µF (Size 0402)
100 pF. A series inductor or small resistor can be placed in R6 for additional C3 = 100 pF (Size 0402)
decoupling. R6 = 0 (Size 0402)
C5 Filter Capacitor. The internal 50 pF averaging capacitor can be augmented C5 = 1 nF (Size 0603)
by placing a capacitance in C5.
C4, R5 Output Loading. Resistors and capacitors can be placed in C4 and R5 to C4 = R5 = Open
load test V rms. (Size 0603)
V GAIN V V DRIFT TEMP C
OUT IN OS VOS
()
++ × °
()
25
The equation can be rewritten to yield a temperature compen-
sated value for V
IN
.
V
V V DRIFT TEMP C
GAIN
IN
OUT OS VOS
=
−− × °
()
()
25
EVALUATION BOARD
Figures 43 and 46 show the schematic of the AD8361 evalua-
tion board. Note that uninstalled components are drawn in as
dashed. The layout and silkscreen of the component side are
shown in Figures 44, 45, 47, and 48. The board is powered by a
single supply in the range, 2.7 V to 5.5 V. The power supply
is decoupled by 100 pF and 0.01 µF capacitors. Additional
decoupling, in the form of a series resistor or inductor in R6,
can also be added. Table V details the various conguration
options of the evaluation board.
AD8361
–15–
REV. A
AD8361
VPOS
IREF
RFIN
PWDN
SREF
VRMS
FLTR
COMM
C1
100pF
R2
75
C5
1
2
3
45
6
7
8
C2
0.01F
RFIN
V
rms
C3
100pF
VPOS
V
S
SW2
V
S
SW3
SW1
A
B
A
B
R5
(OPEN
)
R4
0
1nF
C4
(OPEN
)
R6
0
A
B
TP2
TP1
VPOS
VPOS
Figure 43. Evaluation Board Schematic micro_SOIC
Figure 44. Layout of Component Side micro_SOIC
Figure 45. Silkscreen of Component Side micro_SOIC
Figure 46. Evaluation Board Schematic, SOT-23-6L
Figure 47. Layout of the Component Side, SOT-23-6L
Figure 48. Silkscreen of the Component Side, SOT-23-6L
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